M

Manish Pandey

Software Engineer

Bengaluru, Karnataka, India11 yrs 1 mo experience
Highly Stable

Key Highlights

  • Experienced in ASIC design and digital electronics.
  • Proficient in RTL design and static timing analysis.
  • Strong background in electronic engineering and circuit design.
Stackforce AI infers this person is a skilled ASIC and digital design engineer in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

AsicRtl DesignDigital Design

Other Skills

Analog Circuit DesignApplication-Specific Integrated Circuits (ASIC)Assembly LanguageCC++CDCCommunicationData StructuresDigital DesignsDigital ElectronicsDigital Signal ProcessingElectronic EngineeringElectronicsFull custom IC design ToolsHSPICE

Experience

11 yrs 1 mo
Total Experience
9 yrs 3 mos
Average Tenure
1 yr 10 mos
Current Experience

Qualcomm

ASIC Design Engineer

Jul 2024 – Present · 1 yr 10 mos · Bengaluru, Karnataka, India

ASICStatic Timing AnalysisRTL DesignVerilogDigital Designs

Synopsys

2 roles

ASIC Digital Design Engineer

Aug 2015 – Jun 2024 · 8 yrs 10 mos

ASICDigital DesignRTL CodingVerilogC++

Intern

Feb 2015 – Jul 2015 · 5 mos

Education

Birla Institute of Technology, Mesra

Bachelor of Engineering (BE) — Electronics and Communication Engineering

Jan 2011 – Jan 2015

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