Koshal Sharma

Product Engineer

Bengaluru, Karnataka, India6 yrs 11 mos experience

Highly Stable

Key Highlights

6+ years in Analog Circuit Design and Verification.
Led multiple successful product deliveries.
Expertise in silicon debug and failure analysis.

Stackforce AI infers this person is a skilled Analog Design Engineer with a focus on semiconductor technologies.

Contact

koshal.sharma@ti.com LinkedIn

Skills

Core Skills

Analog Circuit DesignAnalog Design Verification

Other Skills

Amplifier DesignAnalog IC LayoutCC++Cadence VirtuosoDesign VerificationGNU OctaveIntel 8085Keysight's ICCAPLaTeXLoop StabilityMIPS Instruction SetMatlabPIC ProgrammingPSpice

About

Analog Design Lead in the Power Switches Enterprise team at Texas Instruments India. 6+ years of experience in Analog Circuit Design and Verification. Delivered multiple successful products in the past as a lead as well as a designer. Design experience includes Closed Loop Amplifiers, Chopper Amplifier, Bandgaps, Comparators, Timer, POR, OTP NVM, Charge Pump, DAC, LDO Voltage Regulator etc along with top level solutions. Silicon debug background covers the hardware level debugs, systematic failure analysis.

Experience

6 yrs 11 mos

Total Experience

6 yrs 11 mos

Average Tenure

6 yrs 11 mos

Current Experience

Texas instruments

Analog Design Engineer

Jul 2019 – Present · 6 yrs 10 mos · India

Working as an Analog Design Engineer in the Ideal Diode portfolio of the Power Switches group at TI India

System IntegrationCadence VirtuosoAnalog Circuit DesignAnalog Design Verification

Nyu tandon school of engineering

Summer Research Intern

May 2018 – Jul 2018 · 2 mos · New York City

Worked on the compact modeling of Black Phosphorus Field Effect Transistors(BPFETs) in Verilog-A. Implemented the surface potential based numerical model of the BPFET in Verilog-A. Extracted model parameters using Keysight's ICCAP software.

Texas instruments

Analog Intern

May 2017 – Jul 2017 · 2 mos · Bengaluru Area, India

Designed a soft start circuit for 60V and 6A e-Fuse with integrated power-FET. The design included a differential to single ended operational transconductance amplifier, in a non inverting configuration. The amplifier was required to amplify an externally generated ramp so as to drive the gate of an internal power-FET.

Cadence VirtuosoAnalog Circuit Design