BHANU PRATAP

Engineering Manager

Gurgaon, Haryana, India10 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 8 years of experience in FPGA and RTL design.
Expertise in developing secure solutions for safety-critical applications.
Proven track record in leading cross-functional teams.

Stackforce AI infers this person is a Defense and Industrial Automation expert with a focus on FPGA and RTL design.

Contact

bhanupratap.nitg@gmail.com LinkedIn

Skills

Core Skills

Fpga Design ArchitectureDigital SecurityRtl Design

Other Skills

PQCEthernetSystem on a Chip (SoC)Management Professional40G Ethernet100G EthernetSingle Board ComputersVHDLVerilogVivadoAldecARINC 818STANAG3350Xilinx VivadoSystemVerilog

About

Self-orchestrated and motivated Engineering Leader working effectively in a dynamic environment for Logic Fruit Technology(well–established and esteemed organization) which allows me to learn, to implement and to execute and innovative new ideas and to develop new skills and enhance existing ones to a significant extent and in a more professional manner, thereby effectively contributing to the organization’s benefit and, giving me scope for my professional growth.I have overall 8+ years of RTL development, simulation and synthesis experience for FPGA, SBC (single board computers) & SoC-based designs from device selection to end product development, including micro architecture by following DO-254. I have extensive experience with AMD, Altera, Lattice, and Efinix FPGA-based designs, including defence-specific audio, video, security, and communication protocols such as DisplayPort, HDMI/DVI, ARINC 818, STANAG 3550 B, MIL-STD-1553, ARINC 429, 1-100G Ethernet (L3-L5 layers), PCIe, and USB. I also have experience with CNN/Predictive Maintenance-based (AI/ML) solution stacks for IIoT & Industrial Automation, Flash Controller, and Video Mixing (Merging and Overlay). Additionally, I have expertise in architecting FPGA-based security solutions, from Root of Trust (RoT) to runtime security, utilizing PQC algorithms.

Experience

Logic fruit technologies

5 roles

Engineering Manager - FPGA/RTL Design

Promoted

Jul 2025 – Present · 8 mos

As Engineering Manager at Logic Fruit Technologies, I lead FPGA and RTL design projects with a focus on developing secure, high-performance solutions for safety-critical applications. With over 8 years of experience, I specialize in FPGA-based system design, leveraging advanced communication protocols such as ARINC 818, ARINC 429, and MIL-STD-1553 to enhance defense-specific audio and video applications. My work is grounded in compliance with DO-254 standards, ensuring reliability and safety in every project.
I have a proven track record of designing robust FPGA-based security solutions, including the integration of Post-Quantum Cryptography algorithms to strengthen runtime security. My expertise spans architectures for SBCs and SoCs, as well as RISC-V SoC integration using tools like Lattice Radiant and Propel. Passionate about innovation and technical excellence, I collaborate with cross-functional teams to deliver cutting-edge solutions that meet the growing demands of the FPGA market.

Digital SecurityPQCEthernetSystem on a Chip (SoC)Management Professional40G Ethernet+3

Sr. Lead Engineer - FPGA/RTL Design

Apr 2022 – Jul 2025 · 3 yrs 3 mos

Led multiple FPGA design projects, overseeing the transition from micro architecture to system architecture.
Utilized Lattice Radiant for synthesis and Lattice Propel for RISC-V SoC integration, enhancing design efficiency.
Collaborated with cross-functional teams to ensure successful project delivery, contributing to the company’s innovative edge in the FPGA market.

Lead Engineer - FPGA/RTL Design

Promoted

Jul 2020 – Apr 2022 · 1 yr 9 mos

In this role I have started leading a small R&D team to develop various RTL modules for different projects.
I have worked on AVPSM(Arinc818 Video Processing and Switching Module), ARINC818 generator and analyser, ARINC818 SMFD.
I have developed ARINC429 IP and got basic knowledge of various protocols like MIL1553, USB 2.0/3.0, PCIe Gen 2.

R&D Engineer - FPGA/RTL Design

Jul 2018 – Jul 2020 · 2 yrs

In this role, I have started RTL Design & Logic Design for various video & audio processing protocols, and I worked on STANAG, ARINC818, ARINC429 and Video Merging & Overlaying concepts for the AVPSM project.
Project-1: ARINC818 Video Processing and Switching Module(AVPSM) (CLIENT : DRDO)
HDL Languages: VHDL & Verilog
Softwares : Vivado & Aldec, Questasim

R&D Intern

Apr 2018 – Jul 2018 · 3 mos

Developed foundational skills in RTL design as an R&D Intern at Logic-Fruit Technologies.
Gained hands-on experience with VHDL and Verilog for RTL development, simulation, and implementation.
Utilized industry-standard tools such as Vivado, Questasim, and Aldec Riviera Pro to enhance design efficiency.

VHDLRTL DesignARINC 818STANAG3350Xilinx Vivado