Nagulapati Poorna Sai Pavan Kumar — Product Manager
Lead RTL Design Engineer with 7 years of experience delivering high-speed, timing-critical and Radar DSP systems from architecture to hardware validation. Proven expertise in JESD204B/C/D (up to 112 Gbps), deterministic timing (PTP/SyncE Class-C), Multi-chip synchronization, and large-scale digital beamforming (256 beams) across multiple FPGA Platforms (AMD, Altera, Lattice, Efinix, and Achronix).
Stackforce AI infers this person is a specialist in high-speed digital systems and radar signal processing.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Architecture Development
- Radar Application Development
- Jesd204b
- Synchronization
- Data Synchronization
Career Highlights
- Expert in JESD204B/C/D protocols for high-speed systems.
- Proven leadership in radar signal processing projects.
- Strong background in multi-chip synchronization techniques.
Work Experience
Logic Fruit Technologies
Project Lead (2 yrs 11 mos)
Module Lead (2 yrs)
R&D Engineer (1 yr 9 mos)
R&D Engineer Trainee (4 mos)
Education
Bachelor of Technology - BTech at National Institute of Technology , Patna
Intermediate (11th & 12th) at Sri Chaitanya College of Education
5th to 10th at A Little Flower The Leader
Nursery to 4th Class at St.Francis English Medium High School