Amit Prakash

Director of Engineering

Bengaluru, Karnataka, India19 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in NoC and interconnect architecture.
  • Proficient in low power design and optimization.
  • Strong background in post-silicon validation and debugging.
Stackforce AI infers this person is a Semiconductor Design Expert with a focus on low power and high-performance architectures.

Contact

Skills

Core Skills

ArchitectureAnalog Circuit Design

Other Skills

Performance AnalysisDynamic powerStatic powerLow-power DesignVerilogSystem VerilogDigital IC DesignDigital Circuit DesignOVMDram ControllerDDR3Computer ArchitectureAnalog Circuit testingDIB board designXML

About

o NoC/Interconnect Architecture, uArchitecture, design, performance modelling and analyses o Low Power Design, dynamic power analyses and optimization, clock tree power optimization and analyses, static power modelling, wire delay modelling o Fabric/NoC Design verification, Coherent High Speed Interconnect, Dram Controller and sub-system verification o Post silicon validation experience with sharp debug skills therein o Proficient in verilog, system verilog and Object Oriented Programming o Very result oriented with high quality control Specialties: o Proficient in VCS, Modelsim, C++, Python, Matlab, Spice o Mentor engineers in Interconnect, DDR, I/O Analog mixed Signal technical areas

Experience

Qualcomm

Director of Engineering

Feb 2015Present · 11 yrs 1 mo · Greater Bengaluru Area

  • Manage and lead the fabric design team at Bangalore Design Center. It includes but is not limited to the following:-
  • Delivering interconnects/NoC (Network On Chip) solution that bakes in SoC requirements on bus interfacing, power domains, FuSA and performance
Analog Circuit DesignArchitecture

Apple

ASIC Design Engineer

Nov 2012Feb 2015 · 2 yrs 3 mos · Austin, Texas Metropolitan Area

  • Debug, Scandump, DFT, DFD, PCIe phy

Amd

2 roles

Sr Design Engineer

Jan 2012Nov 2012 · 10 mos · Austin, Texas Metropolitan Area

  • AMD DDR2, DDR3 and DDR4 controller

Sr. Product Development Engineer

Jan 2008Dec 2011 · 3 yrs 11 mos · Austin, Texas Metropolitan Area

  • PLL Characterization, test time reduction algorithms, cutting edge process tech debugs on AMD microprocessors. Multiple spot light awards

Carnegie mellon university

Graduate Research Assistant

Sep 2006Dec 2007 · 1 yr 3 mos

  • Worked with Prof. Larry Pileggi on a DARPA funded project and developed a framework for the analyses of phase change memory based reconfigurable system (MISCIC). Also modeled the performance, area and static power consumption of the MISCIC

Ittiam systems pvt ltd

Summer Internship

May 2005Jun 2005 · 1 mo · Bangalore, India

  • Implementing Ogg-Vorbis decoder on the TI DSP processor

Education

Carnegie Mellon University

MS — Electrical and Computer Engg

Jan 2006Jan 2007

Indian Institute of Technology, Kharagpur

B.Tech — Electrical Engineering

Jan 2002Jan 2006

Sainik School Tiliaya

12th Standard — Science

Jan 1995Jan 2002

Stackforce found 100+ more professionals with Architecture & Analog Circuit Design

Explore similar profiles based on matching skills and experience