Jul 2018 – Nov 2019 · 1 yr 4 mos

Jul 2015 – Jun 2018 · 2 yrs 11 mos

Jul 2012 – Jun 2015 · 2 yrs 11 mos

• On a short note, my primary responsibility is the physical design process involving the transformation of Gate Level Netlist description to foundry specified GDSII description involving steps like Floorplanning, Placement, Clock Tree Synthesis, Routing, Static Timing Analysis, Physical Verification (DRC,LVS) for realizing next generation low power AMD APU SoCs.

Sep 2008 – Jul 2010 · 1 yr 10 mos · Bengaluru Area, India

• I was trained as an ASIC Verification Engineer in the VLSI Domain of Wipro. Later I moved into Board Design stream of Wipro. I resigned from Wipro on 9th July 2010, to pursue my higher studies.