Saptarshi Mandal

Software Engineer

Hillsboro, Oregon, United States13 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in semiconductor process innovation and device physics.
Led cross-functional teams to enhance transistor performance.
Developed advanced GaN power transistors for high voltage applications.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on device physics and process innovation.

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Skills

Core Skills

Semiconductor EngineeringTechnology RoadmappingStatistical Data AnalysisDevice Characterization

Other Skills

JSLStatistical ModelingLeadershipTest chip designData MiningDesign of Experiments (DOE)JMPMatlabCAlgorithmsProgrammingSputter DepositionPhotolithographyMOCVDReactive Ion Etching

About

8 years background in developing Intel's leading edge Si CMOS node; Extensive experience in device physics, data and statistical analysis driven decision making, technology roadmap definition and semiconductor process innovation. Over 13 years of experience in semiconductors spanning a wide range of topics from ultra low power synaptic memories for neuromorphic applications to high voltage wide bandgap power semiconductor devices and finally Intel's lead Gate All Around transistors.

Experience

Intel corporation

2 roles

Senior Device Engineer

Promoted

Mar 2022 – Present · 4 yrs

Led cross module teams with DoE and data analysis to enhance transistor performance and product targeting.
Defined roadmap for meeting PDK release criteria for Intel's advanced gate-all-around node.
Responsible for meeting logic transistor performance commitments and PDK release development.

JSLSemiconductor EngineeringTechnology Roadmapping

Device Engineer

Feb 2018 – Feb 2022 · 4 yrs

Analyzed device performance and identified process-driven impacts for Intel's GAA Pathfinding Team.
Developed statistical data analysis and experimental planning for transistor performance improvement.
Designed test chips and contributed to infrastructure developments for device analysis.

Semiconductor EngineeringStatistical ModelingStatistical Data Analysis

University of california, davis

Graduate Research Assistant

Aug 2016 – Dec 2017 · 1 yr 4 mos · Sacramento, California Area

Designed high breakdown voltage GaN power transistors and IMPATT diodes at University of California, Davis.
Conducted device simulation, characterization, and physics-based analysis for novel measurement techniques.
Successfully demonstrated high breakdown voltage GaN vertical transistors and high field diodes.

Semiconductor EngineeringLeadershipDevice Characterization

Arizona state university

Research Assistant

May 2014 – Jul 2016 · 2 yrs 2 mos

Designed transistor layouts, developed processes, and conducted device simulations for high breakdown voltage GaN vertical transistors.
Innovated measurement techniques and performed physics-based analysis for transistors and diodes on wide bandgap materials.

Semiconductor Engineering

University of toledo

2 roles

Research Assistant

Jan 2012 – Dec 2013 · 1 yr 11 mos

Led research on Transition Metal Oxide development for synaptic devices for neuromorphic applications.
Developed processes, characterized TMO Resistive RAMs, and conducted physics-based modeling.
Achieved advancements in neuromorphic technology with potential for real-world applications.
Developed skills in research, process development, device characterization, and physics-based modeling.

Semiconductor Engineering

Teaching Assistant

Aug 2011 – Apr 2012 · 8 mos

Teaching Assistant for Microsystems Design, a senior level course on Microprocessor 80186, for Fall 2011.
Teaching Assistant for Electric Circuits-I, a sophomore course on circuits, for Spring 2012.

Semiconductor Engineering