Mar 2017 – Jan 2019 · 1 yr 10 mos · County Dublin, Ireland

• Senior engineer in the Digital team developing UWB transceiver ICs for Real-Time Location Systems. Responsible for entire spectrum of VLSI front-end design activities from micro-architecture to post-silicon validation.
• Designed the AES/DMA Controller module for encryption/authentication on Decawave's UWB transceiver.
• Enhanced the FPGA prototyping system with improved RF channel modelling and clock gating emulation. Also worked on post-silicon validation and characterisation.

Dec 2015 – Aug 2016 · 8 mos · Eindhoven Area, Netherlands

• Graduate student intern in the IoT team developing a wireless sensor network for air quality monitoring. Worked on coexistence of heterogeneous wireless sensor networks.
• Analysed coexistence between IEEE 802.15.4, BLE and IEEE 802.11 in the unlicensed 2.4 GHz ISM band through MATLAB simulations and real-world experiments. Published results at IEEE IECON 2016.

Apr 2012 – Mar 2014 · 1 yr 11 mos · New Delhi Area, India

• Senior engineer in the VLSI design team developing high-definition video transceiver ICs for the consumer electronics industry. Responsible for entire spectrum of VLSI front-end design activities from micro-architecture to post-silicon validation.
• Designed the Link Control Bus (CBUS) module for the MHL v2.0 PHY IP core on TranSwitch's HDplay high-speed video transceiver.

Jul 2010 – Apr 2012 · 1 yr 9 mos · Hyderabad Area, India

• Senior engineer in the Communications Business Unit developing wireless IPs for tier-1 communications companies. Responsible for entire spectrum of FPGA design activities from micro-architecture to in-circuit testing.
• Designed feature enhancements to Xilinx's PC-CFR wireless IP and ported to Xilinx Virtex-7 and Kintex-7 FPGA families. Achieved a performance of 350 MHz for a 32x scaling from the previous version running at 400 MHz.
• Developed a MATLAB simulator for the IP core for beta-testing and provided active customer support.

Apr 2005 – Mar 2010 · 4 yrs 11 mos · Chennai Area, India

• Senior engineer in the hardware design team developing wireless and wireline communication systems. Responsible for algorithm development, modelling and simulation, FPGA and PCB design activities.
• Designed a 3G DECT baseband PHY, developed the PHY algorithms, modelled and analysed performance through MATLAB simulations. Designed features such as an ISI-optimised RRC filter and an LMS-based adaptive equaliser for channel estimation.
• Designed a 2.5G DECT baseband PHY, developed the PHY algorithms, modelled and analysed performance through MATLAB simulations. Designed features such as IQ imbalance compensation using adaptive decorrelation and generation of quantisation-error-optimised baseband symbols.
• Designed the frame synchronisation module for a 2x2 MIMO WiMAX baseband PHY and implemented it on a Xilinx Virtex-IIPro FPGA.
• Designed an all-digital PLL to synchronise a Base Station Distributor to the Central Office and implemented it on an Altera Cyclone FPGA. Also involved in the BSD PCB design and bring-up.
• Involved in designing a 2.5G DECT radio tester and implemented it on a Xilinx Spartan-3E FPGA. Designed features such as a multi-frequency counter to measure the accuracy of various clocks in the system.
• Involved in designing an Ethernet over PDH mapper IP core that implements ITU-T G.8040 compliant GFP, G.7043 VCAT and G.7042 LCAS and implemented it on an Altera Cyclone-II FPGA.
• Involved in designing an E1 to SDH mapper IP core that integrates an ITU-T G.707 compliant 4-E1 mapper, G.704 4-E1 framer and a 256x256 Time-Slot Interchanger and implemented it on a Xilinx Spartan-3 FPGA.
• Involved in the PCB design and bring-up of a multi-purpose Smart Network Interface Controller.