Ramya R.

Software Engineer

Hyderabad, Telangana, India8 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in RTL design and verification for FPGAs.
Hands-on experience with advanced digital design tools.
Proficient in implementing complex signal processing algorithms.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with strong FPGA and digital design capabilities.

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Skills

Core Skills

Ip VerificationDigital DesignSignal ProcessingDigital Signal ProcessingRtl Verification

Other Skills

Logic SynthesisVery-Large-Scale Integration (VLSI)IP designMemory validationNetwork on Chip IP verificationVerilog HDLDSP48E2 MacrosEmbedded SystemsUniversal Asynchronous Receiver/Transmitter (UART)DesignDesign Verification TestingHardware DesignHardware Description LanguageVHDLRTL Coding

About

Professional Exposure: Handa on experience in digital design and verification •Tools : vivado, cadence virtuoso, Libero synthesis: design compiler, synplify simulation: Questasim, cadence xcelium STA : primetime - involved in architecture discussion and design of micro architecture. • Hands-on experience in RTL design for real time signal processing algorithms. - worked on video codecs h264,h265 standards. • Working on embedded processors such as Micro Blaze, Zed board & Zynq Ultrascale, RFSoC , MPSoC & 7 series FPGA's. - worked on Xilinx,Intel and microchip FPGAs. • Experience in Firmware development for VGA,UART, I2C, SPI, FIFO and AXI. • Micro architecture designing and timing analysis •Hands on experience in RTL front end checks for Lint, CDC,RDC. • Experience in interfacing industry standard high speed ADC, clock synchronizer and DAC with FPGA. Data acquisition system for ADC and DAC •Experience in ARM processor c coding for PS to PL communication. • Implementation of designs with multiple clock domains •knowledge on TCL,python,perl Experience in using serial port on FPGA to monitor firmware (embedded sw) prints for debug & for writing/reading memory locations on FPGA.

Experience

Microchip technology inc.

Senior RTL design engineer

Nov 2021 – Present · 4 yrs 4 mos · Hyderabad, Telangana, India · On-site

Key Responsibilities:
1. IP design and verification
2. worked on MiV processor for applications.
3. Worked on DSP blocks and Memory blocks like LSRAM, DPSRAM,QPSRAM.
3. Worked on Memories like DDR3,DDR4, LPDDR4 validation and verification.
4. Worked on Network on Chip IP verification and Hardware debugging.
5. Developing testbenches using Verilog/System Verilog and validation designs in simulation environment using BFM/VIP.
testcases development, functional coverage, debugging regression analysis, pumping traffic between Multi IPs. Worked on implementation of AXI Master RTL.

Logic SynthesisVery-Large-Scale Integration (VLSI)IP VerificationDigital Design