Sai Teja Ch — Software Engineer

•Overall 7+ years of experience in Vlsi industry. • 4+ years of relevant experience in Pre-Si Validation, SoC Emulation platform • 3Years of experience in FPGA Design & Validation • Hands on Experience in Verilog , VHDL, System Verilog • Working experience with FPGA Design. • Familiar with Zynq family FPGA's, Vertex-5, Vertex-7 FPGA's, Altera FPGA's • Good understanding of protocols like UART,AMBA AHB, APB • Knowledge on Python and C • Sound knowledge on the functional Simulators like Model-sim, Questa-sim and fpga tools like Xilinx ISE & Xilinx Vivado, Quartus prime • Hands on Working experience with Emulators like Mentor Veloce, Cadence palladium, Protium. •Good debugging experience with transactor logs and waveform debug tools Verdi. • Willing to learn new skills and ability to learn fast • Good debugging and Documentation skills • Good communication skills

Stackforce AI infers this person is a VLSI and FPGA validation expert with strong emulation skills.

Location: Hyderabad, Telangana, India

Experience: 8 yrs 10 mos