ALKA SHARMA

DevOps Engineer

Bengaluru, Karnataka, India11 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 10 years of experience in chip design.
  • Expertise in AI SoC design and integration.
  • Proficient in RTL to GDS processes.
Stackforce AI infers this person is a semiconductor design expert with a focus on AI and FPGA technologies.

Contact

LinkedIn

Skills

Core Skills

Soc DesignMicro-architectureFpga DevelopmentAsic DevelopmentSystem Design

Other Skills

Board DesignCC++CMOSCadence VirtuosoClockCustomer ServiceDebuggingEmulationEnglishFPGA DesigningField-Programmable Gate Arrays (FPGA)GPIO micro-architectureIntegrated Circuit DesignInterrupt

About

AI SoC Engineer with 10 years of experience in end-to-end chip design, from RTL to GDS. Currently part SoC design and integration for Intel’s AI products, including the Xeon roadmap, with expertise spanning RAS, clock and GPIO micro-architecture, synthesis, LEC, and CDC.

Experience

Intel corporation

2 roles

AI SOC Engineering

Jan 2025 – Present · 1 yr 2 mos

  • Micro-Architect for GPIO along with SOC design for RAS, Interrupt, Clock for AI SOC. SOC Integration, Front End Collateral
GPIO micro-architectureSoC designRASInterruptClockSoC Design+1

Logic Design Engineer

Jul 2020 – Aug 2025 · 5 yrs 1 mo

  • Logic Design Engineer, SoC Design
SoC Design

Western digital

Staff Engineer

Feb 2020 – Jul 2020 · 5 mos · India

  • Staff Engineer, Flash Products Groups, ASIC Development Engineering

Xilinx

Design engineer 2

Oct 2017 – Feb 2020 · 2 yrs 4 mos · Hyderabad, Telangana, India

Lattice semiconductor

2 roles

Senior System Design Engineer

Promoted

Mar 2016 – Sep 2017 · 1 yr 6 mos · Hyderabad Area, India

  • Responsible for developing System Use Case for Lattice Upcoming FPGA. Includes developing Specification , RTL Developments to GDS, Support to Verification Team and Silicon level System Bring-Up and Board Design.
  • Currently Working on Machine Learning Use Case Development
System Use Case DevelopmentSpecification DevelopmentRTL DevelopmentVerification SupportSilicon Level System Bring-UpBoard Design+2

System Engineer

Mar 2015 – Mar 2016 · 1 yr · Hyderabad Area, India

  • System Level Board Designing, Emulation, Pre-silicon validation and Post Silicon Validation
System Level Board DesigningEmulationPre-silicon validationPost Silicon ValidationSystem Design

Silicon image

2 roles

System Engineer

Sep 2014 – Mar 2015 · 6 mos · Hyderabad Area, India

  • FPGA Designing, System Level Testing and Debugging, RTL
FPGA DesigningSystem Level TestingDebuggingRTLFPGA Development

Intern System Engineering

Mar 2014 – Aug 2014 · 5 mos · Hyderabad Area, India

  • Pre and Post Silicon Validation

Education

Malviya National Institute of Technology, Jaipur

MASTERS OF TECHNOLGY — VLSI DESIGN

Jan 2012 – Jan 2014

THAKRAL COLLEGE OF TECHNOLOGY, RGTU

Bachelor of Engineering (BEng)

Jan 2008 – Jan 2012

MAHARISHI CENTRE FOR EDUCATIONAL EXCELLENCE.BHOPAL,MP

Jan 2000 – Jan 2008

Stackforce found 26 more professionals with Soc Design & Micro-architecture

Explore similar profiles based on matching skills and experience

AK

Ashish Khicha

Asic Engineer Sr. Staff

at Juniper Networks

Bengaluru, India14 yrs 6 mos exp
Integrated Circuit DesignRTL Design
Lalit singh

Lalit singh

Staff Design Engineer

at Arm

Bengaluru, India11 yrs 6 mos exp
5G technologyASIC IP/SOC designASIC RTL DesignFPGA DesignHardware Engineering
Abhishek Aggarwal

Abhishek Aggarwal

Staff Design Engineer

at Renesas Electronics

Delhi, India9 yrs 6 mos exp
System ArchitectureLow-power DesignASIC Design
Adithya Ranganathan

Adithya Ranganathan

GPU Architect

at NVIDIA

Bengaluru, India9 yrs 4 mos exp
CPU ArchitectureGPU ArchitectureGPU DesignPower ManagementResearch
Baranidharan Sivapatham

Baranidharan Sivapatham

Vice President : FPGA

at Barclays

Singapore, Singapore20 yrs 8 mos exp
ASICFPGASRESoCTrading Platforms
Sanjay Gupta

Sanjay Gupta

Chief Development Officer & India Country Head

at L&T Semiconductor Technologies

South Delhi, India28 yrs 9 mos exp
SemiconductorsEngineering ManagementR&DAutomotiveProduct Development
Navneet Goel

Navneet Goel

Senior Design Verification Engineer (L64)

at Microsoft

Delhi, India12 yrs 3 mos exp
Embedded SystemsLeadershipSoCSubsystem DebugSystem Verilog
Mohammad Safiullah

Mohammad Safiullah

Technical Leader

at Cisco

San Francisco, United States21 yrs 8 mos exp
TelecommunicationsASICFPGA