Venkatramana Gajavelli — Software Engineer
Experienced SOC Design Verification Lead with a strong track record in DDR SoC feature-to-silicon validation for LPDDR4 and LPDDR5. Successfully executed 8+ projects as a DDR SoC DV lead, including leadership of GCC SoC and core teams. Core Expertise: DDR Protocols: LPDDR4, LPDDR5 Bus & Interface Protocols: AHB, AXI, MIPI, HDMI 2.0a, SPI Verification Methodologies: System Verilog, UVM Coverage-Driven Verification: Functional coverage, test planning, and execution VIP Development: Built SPI VIP from scratch using UVM methodology Key Contributions: Developed comprehensive verification test plans and environments in SV/UVM Created and executed tests aligned with coverage goals Delivered high-quality verification closure for multiple SoC projects Holds a valid US B1/B2 Visa.
Stackforce AI infers this person is a highly skilled engineer in the semiconductor and VLSI industry.
Location: Hyderabad, Telangana, India
Experience: 11 yrs 8 mos
Skills
- Ddr Protocols
Career Highlights
- Led 8+ successful DDR SoC validation projects.
- Expert in LPDDR4 and LPDDR5 protocols.
- Developed SPI VIP from scratch using UVM.
Work Experience
Qualcomm
Staff Engineer (1 yr 4 mos)
Senior Lead Engineer (3 yrs)
Senior Engineer (3 yrs 1 mo)
Synaptics Incorporated
ASIC Verification Engineer-2 (1 yr 9 mos)
ASIC Verification Engineer (1 yr 6 mos)
Hidden View Solutions
Embedded Engineer (11 mos)
Education
Master’s Degree at National Institute of Technology Warangal
Bachelor's Degree at Jawaharlal Nehru Technological University
at CELESTIAL MODEL HIGH SCHOOL