Jan 2022 – Aug 2024 · 2 yrs 7 mos · Penang, Malaysia

• Worked on DDRPHY design verification for LPDDR5 and DDR5.
• Good exposure to System Verilog Assertions(SVA), DDR protocols.
• Worked on multiple test chips and products(LunarLake, PantherLake) for verification of DDRPHY functionalities.

Dec 2020 – Jan 2022 · 1 yr 1 mo

• Worked as block level Design Verification Lead for next-generation Adreno GPU used in Snapdragon SOC.
• Contributed to several products of A6x and A7x generations of Adreno GPU.
• Trusted with ownership of Primitive Composer and Rasterizer blocks for complete planning and execution.
• Responsibilities included block ownership, resource planning, risk analysis, understanding specification, coordinating with Design and Architecture teams at multiple sites, verification sign off.
• Responsible for building complete verification strategy and environment, developing test plans, coverage analysis and closure, test bench development(checkers, sequence, components), debugs and reproducing silicon bugs.
• Gained experience on Constrained Random Verification with UVM, formal techniques using Formal Property Verification(FPV), Formal Equivalence Check.

Dec 2017 – Dec 2020 · 3 yrs

Jul 2016 – Nov 2017 · 1 yr 4 mos

Jun 2013 – Jun 2014 · 1 yr · Noida Area, India

• Worked on Linux Kernel, kdbus and Binder IPC mechanisms, NodeJS