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Archi Srivastava

Software Engineer

Noida, Uttar Pradesh, India7 yrs 10 mos experience
Highly Stable

Key Highlights

  • Over three years of experience in semiconductor validation.
  • Strong expertise in Python and USB technologies.
  • Proven ability to enhance electronic device performance.
Stackforce AI infers this person is a Semiconductor Validation Engineer with strong programming and validation skills.

Contact

Skills

Core Skills

PythonUsb3.0Analog Ip Design

Other Skills

Python (Programming Language)Layout design40nm CMOSPhysical verificationUSB2.0C (Programming Language)PvtFunctional validationVerilogLog AnalysisIEEE 802.11VT performanceVoice over IP (VoIP)Session Initiation Protocol (SIP)Algorithms

About

As a Senior Validation Engineer at STMicroelectronics, I leverage my Bachelor of Technology in Electronics and Communications Engineering to ensure the quality and reliability of cutting-edge semiconductor products. With over three years of experience in this role, I have developed strong skills in Python programming, USB3.0, and USB2.0 technologies. Prior to joining STMicroelectronics, I worked as an Engineer and an Associate Engineer at Qualcomm, where I gained valuable experience in software development and testing. I am passionate about applying my technical expertise to create innovative solutions that enhance the performance and functionality of electronic devices.

Experience

Qualcomm

Senior Lead Engineer

May 2025Present · 10 mos · Noida, Uttar Pradesh, India · On-site

Stmicroelectronics

Senior Validation Engineer

Jan 2022May 2025 · 3 yrs 4 mos · Greater noida

Python (Programming Language)USB3.0Python

Qualcomm

2 roles

Engineer

Promoted

Nov 2020Dec 2021 · 1 yr 1 mo

Associate Engineer

Dec 2018Nov 2020 · 1 yr 11 mos

Zs associates

Business Technology Analyst

Aug 2018Nov 2018 · 3 mos · Gurgaon, Haryana, India

  • Sales Crediting (Incentive Compensation : Team Project)
  • Adaptive to Cloud Strategies based on AWS (Amazon Web Services).
  • Technical knowledge on EC2, RedShift, S3.
  • Good knowledge in relational and NoSQL databases like MySQL, SQLServer, Oracle,Postgre RDBMS.
  • Possess working knowledge with SQlite with Python.
  • Worked on various operating systems like Linux, Ubuntu, Windows.
  • Proficient knowledge of Linux bash scripting.
  • Extensive work on MS Office tools like Excel,PowerPoint and Word.
  • Good knowledge of full Software Development Cycle(SDLC) stages in a Waterfall and Agile environment.
  • Possess high working qualities with good interpersonal skills, high motivation, fast learner, good team player and very proactive in problem solving to provide best solutions.

Nxp semiconductors

Intern

Jan 2018Jun 2018 · 5 mos · Noida Area, India

  • Projects :
  • Layout design of analog blocks like Operational amplifier, digital gates in 40nm CMOS.
  • LEF (Layout Exchange Format) generation of analog IPs.
  • View generation of analog IPs to create all the views defined in FAM baseline flow.
  • IPDEV validation of generated views. Views generated in IPDSS standards.
  • Automation in multi PVT support.
  • Duties :-
  • Worked on 40 nm CMOS technology.
  • Be familiar with the Analog IP design procedure.
  • To have hands-on with tools used in Analog IP design process.
  • To learn the layout design techniques for Analog IP (device and routing matching, electromigration,Shielding,Latchup, etc).
  • To get acquainted with different issues (EM, antenna effect, latch up) during layout design.
  • To design layouts for different blocks and circuits of Analog IP.
  • To get knowledge of different physical verification checks (DRC/LVS/DFM) implemented on the designed layout.
  • To develop professional and organizational behavior and be capable of handling real time problem.
  • To generate views such as lef,lpe,celtic,voltus,redhawk(physical and cdev),liberty(prelayout and postlayout),ndm,milkyway and
  • upf for analog IPs.
  • To do IPDEV validation of all the generated views.
  • To view the report of failure and to fix the errors in view generation process.
  • To set IP parameters and set PVT configuration and power/ground pin configuration of IPs for view generation.

Education

Indian Institute Of Information Technology Allahabad

Bachelor of Technology

Jan 2014Jan 2018

Maharshi Patanjali Vidya Mandir

Intermediate — PCM

Maharshi Patanjali Vidya Mandir

High School

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