Rachit Garg

CTO

San Francisco, California, United States11 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in deep learning architecture and optimization.
  • Key contributor to Nvidia's MLPerf training submissions.
  • Strong background in hardware design and software integration.
Stackforce AI infers this person is a Deep Learning Architect with expertise in AI/ML and hardware optimization.

Contact

LinkedIn

Skills

Core Skills

Deep Learning ArchitectureMachine Learning HardwareGpu ArchitectureDeep Learning OptimizationHardware DesignSoftware IntegrationPerformance AnalysisEvent OrganizationFpga Design

Other Skills

Deep learning algorithmsperformance/power optimizationworkload characterizationparallel computingcomputer architectureGPU-SM efficiencypower optimizationperformance optimizationarea tradeoffsHW SW CodesignSQL in Silicon productsPower benchmarkingPerformance benchmarkingOrganizing challengesImage recognition

About

Deep learning algorithms, performance/power optimization and workload characterization of deep neural networks, parallel computing, computer architecture, machine learning hardware. Experience with working on Hardware Design, Architecture and Software Stack for Deep Learning workloads.

Experience

Nvidia

2 roles

Senior Deep Learning Architect

Promoted

Sep 2020 – Present · 5 yrs 6 mos

  • Re-inventing the architecture across the hardware and software stack for training Large Language models at the speed of light.
  • One of the key contributors to Nvidia’s winning MLPerf training submissions over the years.
Deep learning algorithmsperformance/power optimizationworkload characterizationparallel computingcomputer architecturemachine learning hardware+2

Senior ASIC Engineer

Nov 2017 – Sep 2020 · 2 yrs 10 mos

  • Making GPU-SM more efficient (power, performance and area tradeoffs) for graphics/DL/ML workloads.
GPU-SM efficiencypower optimizationperformance optimizationarea tradeoffsGPU architectureDeep learning optimization

Oracle

Hardware Design Engineer

Jun 2016 – Nov 2017 · 1 yr 5 mos · Santa Clara, California

  • HW SW Codesign for SQL in Silicon products from Sun Microsystems
HW SW CodesignSQL in Silicon productsHardware designSoftware integration

Qualcomm

Engineering Intern

May 2015 – Aug 2015 · 3 mos · Greater San Diego Area

  • Power and Performance benchmark for Snapdragon.
Power benchmarkingPerformance benchmarkingPerformance analysis

Purdue university

Graduate Research Assistant

Feb 2015 – May 2015 · 3 mos · West Lafayette

  • Organized the first Low Power Image Recognition Challenge held in Design Automation Conference (DAC)
Organizing challengesImage recognitionEvent organization

Freescale semiconductor

Design Engineer

Jan 2013 – Aug 2014 · 1 yr 7 mos · Noida Area, India

  • FPGA, RTL, Memory Controllers
  • Hardware Software codesign.
FPGARTLMemory ControllersHardware Software codesignFPGA designHardware design

Education

Purdue University

Master of Science (MS) — Computer Engineering

Indian Institute Of Information Technology Allahabad

B.Tech (Hons.) — Electronics and Communications Engineering

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