Satnam Singh

Software Engineer

Los Altos, California, United States34 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in functional programming and hardware verification.
  • Significant experience in machine learning chip design.
  • Strong background in teaching and research in computing.
Stackforce AI infers this person is a Semiconductor and Software Engineering expert with a focus on hardware design and verification.

Contact

LinkedIn

Skills

Core Skills

Machine LearningFormal VerificationFunctional ProgrammingTheorem ProvingHardware DesignCompiler OptimizationConfiguration ManagementDistributed ComputingFpga DesignEducation

Other Skills

LeanSystemVerilogLLMsCoqFPGAsTensorflowXLAHaskellBluespecVerilogDalvik bytecodeProGuard DSLAPIsKubernetesDocker

About

At Harmonic I am working on applying machine learning and theorem proving with Lean to the formal verification of hardware. Previously at Groq I applied the power of functional programming languages to the design of machine learning chips and their programming models. Previously I worked at Google (machine learning chips, cluster management), Facebook (Android optimization), Microsoft (parallel and concurrent programming) and Xilinx (Lava DSL for hardware design, formal verification of hardware). I started his career as an academic at the University of Glasgow (FPGA-based application acceleration and functional programming, software-defined radio). My research interests include functional programming in Haskell, high level techniques for hardware design (Lava, Bluespec, DSLs in Haskell, Coq and C#), formal methods (SAT-solvers, model checkers, theorem provers), formally verified hardware/software co-design, FPGAs, and concurrent and parallel programming. I am a Senior Member of the ACM and IEEE and a Fellow of the IET. I am also an elected member of IFIP WG2.8 (functional programming) and IFIP WG2.11 (program generation). Previously I served as an elected member of ACM SIGPLAN. I held held part-time or honorary positions at The University of Birmingham, Imperial College London, the University of Washington, and the University of Santa Cruz (UCSC).

Experience

Harmonic

Software Engineer

Nov 2025 – Present · 4 mos · Palo Alto, California, United States · On-site

  • Applying machine learning and the Lean interactive theorem prover to the formal verification of hardware.
machine learningLeanformal verification

Groq

Fellow

Oct 2021 – Jun 2025 · 3 yrs 8 mos · Mountain View, California, United States

  • Applying functional programming to the design of silicon chips for machine learning. SystemVerilog RTL implementation of key features of the V2 Groq LPU (custom silicon chip for very fast machine learning inference). Formal hardware verification using both model checking (SystemVerilog Assertions, Jasper Gold, YosysHQ) as well as theorem provers (Agda). Using LLMs to prove formal properties of hardware.
functional programmingSystemVerilogformal verificationtheorem provingLLMs

Google

Software Engineer, Google AI and Research

Feb 2019 – Sep 2021 · 2 yrs 7 mos · Mountain View

  • Enclave-based support for security and privacy. Formally verified hardware for silicon root of trust (RoT). Theorem proving, Coq, SystemVerilog, FPGAs, functional programming in Haskell), open-source hardware.
  • Previously making machine learning go faster. Compilers for special purpose hardware. Making much use of Tensorflow and XLA.
theorem provingCoqSystemVerilogFPGAsfunctional programmingTensorflow+1

X, the moonshot factory

Software Engineer

Mar 2017 – Feb 2019 · 1 yr 11 mos · Mountain View, California

  • Having much fun writing Haskell and Bluespec for hardware design every day, wrestling with Verilog/System Verilog, and trying to accelerate algorithms by computing without processors.
HaskellBluespecVerilogSystemVeriloghardware design

Facebook

Software Engineer

Aug 2015 – Mar 2017 · 1 yr 7 mos · Menlo Park, California, USA.

  • Android mobile performance improvement through low level Dalvik bytecode optimizations to improve the performance of Facebook Android applications. Re-implementation of the ProGuard DSL for specifying reflection and its matching engine. Compiler optimization passes and general compiler infrastructure.
Dalvik bytecodecompiler optimizationProGuard DSL

Google

Software Engineer

Jan 2012 – Aug 2015 · 3 yrs 7 mos · Mountain View, California

  • Configuration management (distributed key-value store, YAML specification processing); APIs (notification/webhooks); analytics infrastructure (Google Analytics, dashboards, logs processing); Kubernetes (open source containers, Docker, fluentd, Elasticsearch, LogStash, Kibana).
configuration managementAPIsKubernetesDocker

University of birmingham

Professor of Reconfigurable Systems

Oct 2006 – Dec 2011 · 5 yrs 2 mos · Birmingham, England, United Kingdom · On-site

  • Researched novel ways of designing and verifying digital circuits.
designing digital circuitsverifying digital circuitshardware design

Microsoft

Director, Principal Architect and Senior Researcher

Feb 2004 – Nov 2011 · 7 yrs 9 mos · Redmond USA and then Cambridge, United Kingdom

  • Microsoft: High level models for distributed computing; libraries for concurrent programming; software transactional memory.
  • Microsoft Research: High level synthesis to FPGAs; formal verification; hardware/software co-design; GPGPU.
distributed computingconcurrent programminghigh level synthesis

Xilinx

Principal Architect

Jan 1998 – Jan 2004 · 6 yrs · San Jose, California

  • High level FPGA design tools and verification.
FPGA design toolsverificationFPGA design

Compass design automation / vlsi technology

Engineer

Jun 1991 – Sep 1991 · 3 mos · Sophia Antipolis, France

  • Microcode synthesis for data-path controllers for VLSI design tools.
microcode synthesis

University of glasgow

Lecturer

Jan 1991 – Dec 1997 · 6 yrs 11 mos · Glasgow, UK

  • I held a permanent position as a lecturer first in the Dept. Electronics and Electrical Engineering and then in the Dept. of Computing Science. I managed research projects funded by EPSRC and the DoD on reconfigurable systems and I was actively involved in teaching and administration.
teachingresearch project managementeducation

European silicon structures (es2)

Engineer

Jun 1987 – Sep 1987 · 3 mos · Bracknell, UK

  • CAD tool software for chip I/O configuration and placement.
CAD tool software

Education

University of Glasgow

PhD — Computing Science

Jan 1987 – Jan 1991

University of Glasgow

BSc — Computing Science

Jan 1983 – Jan 1987

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