Chandan Karfa

Associate Consultant

Bengaluru, Karnataka, India14 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in High-level Synthesis and FPGA Logic Synthesis.
  • Significant experience in EDA and Formal Verification.
  • Strong academic background with a PhD from IIT Kharagpur.
Stackforce AI infers this person is a highly skilled professional in EDA with expertise in FPGA and ASIC technologies.

Contact

Skills

Core Skills

High-level SynthesisFpga Logic Synthesis

Other Skills

ASICAlgorithm DesignAlgorithmsApplication-Specific Integrated Circuits (ASIC)CC++Data StructuresDebuggingDigital ElectronicsEDAEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)Formal VerificationGCC

About

1. Currently working as Associate Professor @ CSE, IIT Guwahati. 2. Worked as Assistant Professor @CSE, IIT Guwahati for 5years. 2. Worked as Sr R&D Engineer in Synopsys (India). for almost five years in High-level Synthesis and FPGA Logic Synthesis tools. 3. Completed MS and PhD from IIT Kharagpur. 4. Primary research interests are in Formal Verification, high-level synthesis and its verification, EDA, and Verification of Compiler Optimizations.

Experience

Indian institute of technology, guwahati

2 roles

Associate Professor

Promoted

Oct 2021Present · 4 yrs 5 mos

Assistant Professor

Aug 2016Nov 2021 · 5 yrs 3 mos

Synopsys

Sr R&D Engineer

Sep 2011Jul 2016 · 4 yrs 10 mos

  • I have worked on the Synphony Model Compiler, used for translating Matlab Simulink models to RTL targeted at FPGA as well as ASIC platforms. My responsibilities was planning and development of new features in SMC as well as enhancement of the existing global optimizations such as retiming and folding. I have worked on major projects like automatic register balancing, memory inference from Matlab code, Multi-cycle path support in SMC and various retiming related projects.
  • Currently, I am working in the Synplify FPGA logic synthesis tools. My primary responsibility is to improve QoR of the tool. I am working on improvement of RAM mapping, replication and GCC related projects of the product.
High-level SynthesisFPGA Logic SynthesisMatlabRTLQoRRAM mapping+1

Education

Indian Institute of Technology, Kharagpur

Doctor of Philosophy (Ph.D)

Jan 2008Jan 2011

Indian Institute of Technology, Kharagpur

Master of Science (by Research); Department — High-level Synthesis and its Verification

Jan 2005Jan 2007

University of Kalyani

Bachelor of Technology — Information Technology

Jan 2000Jan 2004

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