Jun 2014 – Aug 2017 · 3 yrs 2 mos · Seattle, WA

• Employee #5 and only data scientist for the first 1.5 years. Then, recruited and led a team of data scientists to develop and implement dozens of machine-learned models, several recommendation systems, ad-based survey systems for use in e.g. brand-lift campaigns, and various analytics reports. Optimized data collection system to maximize the amount of useful data extracted per device session, normalize data collected across multiple data partners, and find fraud and errors in these sources.

Oct 2010 – May 2014 · 3 yrs 7 mos

• WWAN modem power lead. Responsible for meeting power consumption requirements of LTE, UMTS, HSPA, 1x/DO, TD-SCDMA and GSM/EDGE modems from conception through tape-out and commercialization.

Feb 2009 – Oct 2010 · 1 yr 8 mos

• GPS Power Lead. Achieved a 6x reduction in GPS power consumption. Shipping in hundreds of millions of smartphones worldwide.
• Coordinated power optimizations across digital, analog, and RF hardware, software, and algorithms teams at multiple sites internationally. Assessed cost, performance, and time-to-market tradeoffs with power consumption.
• Developed power model of end-to-end GPS use cases, such as 1Hz tracking, including power management, RF, and digital baseband ICs.
• Worked with product marketing and key customers to develop multi-year power roadmap, including power targets for novel use cases in development.
• Evaluated technology and IP for potential acquisitions.

Aug 2007 – Feb 2009 · 1 yr 6 mos · Cambridge, MA

• Drove power reduction of the mobile WiMax system including RF/Analog and Digital ASICs. Improved standby power by 3x and active power by 2x.
• Built a high-level power estimation tool for digital ASICs to explore low power techniques such as voltage scaling, power gating, data retention voltages, clock gating, and memory optimization.
• Designed and implemented flexible decimation filter including CIC decimator, digital NCO, and fractional rate converter meeting stringent jammer blocking specs.
• Set low power agenda for quarterly Technical Advisory Board meetings. Held monthly meeting with MIT Professor, Anantha Chandrakasan, on advanced power reduction techniques.

Feb 2006 – Feb 2009 · 3 yrs

• Director of the Circuits and Communication Research Lab with research programs on: sensor networks, MIMO and multi-antenna systems, adaptive and cognitive radios, and reconfigurable and reliable circuit architectures for multi-mode wireless devices.
• Supervised several graduate and undergraduate researchers. Procured $300K single-Primary Investigator grant from the Semiconductor Research Corporation.
• Developed new curriculum for digital VLSI instruction at UW at the graduate and undergraduate level. Incorporated new elements of deep-sub-micron process technology. Updated design projects to use state-of-the art CAD tools.
• Coordinated CAD support effort for 10 courses and 6 research groups.
• Organized well-attended seminar series of 10 speakers from industry and academia.

Jun 2005 – Jan 2007 · 1 yr 7 mos

• Specialized in mapping wireless physical layer basebands to a proprietary low-power scaleable processor family. Implemented various low-level physical layer operations for 802.11a/b/g/n and 802.16a/e protocols, including: digital filtering, low-IF translation, I/Q imbalance, DC offset, AGC, carrier frequency estimation, timing estimation, and frequency domain equalization.
• Invented novel configurable physical interface to RF integrated circuits, including
• DigRF 3G compliant devices. Filed patent on same.
• Presented technology to prospective VCs conducting due diligence.

Jan 2005 – Dec 2005 · 11 mos

• Developed web-based distance learning program for industry engineers consisting of 12 multi-media short courses in CS and EE. Consulted with VPs of Engineering at various technology companies to identify both the appropriate content and appropriate delivery mechanism for industry engineers to update skills to latest technology. View at: https://globe.berkeley.edu/login/index.cfm.
• Managed external web development consultants and 6 internal course content developers. Negotiated contracts; set and tracked budgets.

Jan 2005 – Jun 2005 · 5 mos

• Performed research on: co-design of physical and media-access (MAC) layers for low
• power sensor network nodes, and co-design of synchronization with oversampling
• ADCs.

Jul 1999 – Dec 2004 · 5 yrs 5 mos

• Reduced synchronization subsystem energy and convergence time by a factor of 4 by developing a low power design methodology with a focus on wireless sensor network nodes.
• Designed 300uW synchronization system for wireless sensor network modem. Explored digital vs. analog implementation tradeoffs, and prototyped using Xilinx FPGA and Anadigm FPAA (analog FPGA). Coded and synthesized VHDL module of algorithm’s digital portion for inclusion on protocol processor ASIC.
• Designed, implemented, and tested digital timing recovery and synchronization processor for a 1.6 Mb/s DSSS QPSK, TDMA wireless communication device in a 600,000-transistor 0.18um design.
• Developed novel fast and accurate gate-level power estimation methodology using Synopsys Power Compiler. Within 15% accuracy and over 50x faster than traditional transistor level methodology.

Jun 2002 – Aug 2002 · 2 mos

• Conducted due diligence of potential investment companies including technical feasibility and market sizing. Participated as technical evaluator in partner meetings on investment decisions. Attended board meetings of portfolio companies.
• Completed technology roadmap of wireless space including technology survey and market research to identify business opportunities in cellular 3G systems, wireless LAN, and wireless PAN.

Jan 2000 – Dec 2002 · 2 yrs 11 mos

• Drove specification of analog subsystem in close collaboration with external vendor and three internal groups (RF hardware, Digital Hardware, and Software), all in different cities and on two continents.
• Performed some of the earliest experiments on the interference between Bluetooth and 802.11b. Developed C++ software to model wireless physical layer interference. Integrated with MAC layer models (developed by NIST) for delivery to IEEE 802.15.2 task group on coexistence. Presented model at task group meeting.

Jul 1997 – Dec 2000 · 3 yrs 5 mos

• Single handedly designed prototype of a projection-capable single-panel LCOS display architecture as masters thesis. Demonstrated architecture feasibility. All follow-on display architectures to date incorporate elements of this design.
• Designed variety of circuit blocks for seven liquid-crystal-on-silicon display substrates, including the world’s first 1080p single-panel LCOS display.
• Produced custom layout of critical analog components: DACs, ADCs, PLLs. receivers.