Manoj Sharma

Software Engineer

Noida, Uttar Pradesh, India20 yrs 8 mos experience

Highly StableAI Enabled

Key Highlights

Over 20 years in validation and emulation workflows.
Expert in architecting complex SoC designs.
Innovative use of AI to enhance validation efficiency.

Stackforce AI infers this person is a leader in semiconductor validation and emulation, specializing in complex SoC architectures.

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Skills

Core Skills

EmulationValidationVerificationIntegrationTransactor DevelopmentArchitectureDesign

Other Skills

ASICAlteraAnalogApplication-Specific Integrated Circuits (ASIC)Computer ArchitectureDDRDFTDebuggingDigital DesignEDAEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)Functional VerificationGenerative AI

About

With over 20 years of experience in pre-silicon and post-silicon validation, I specialize in architecting and optimizing emulation-based workflows across platforms like ZeBu, Palladium, Veloce, and FPGAs. I’ve led global initiatives in developing UFS and eMMC transactors, memory models (LPDDR, DDRx, NAND/NOR Flash), and emulation infrastructure for complex PowerPC-based SoCs. I spearhead the development and optimization of emulation methodologies, integrating generative AI techniques to enhance efficiency, scalability, and automation. My focus is on accelerating debug cycles, improving test coverage, and reducing turnaround time—especially for low-power and DFT test cases. With hands-on expertise in UVM-based environments, synthesizable VIPs, and lab-level debugging using oscilloscopes and logic analyzers, I bring a holistic approach to validation. My passion lies in driving innovation and enabling robust validation of high-speed, mixed-signal SoC designs.

Experience

Qualcomm

Senior Staff Engineer

Jul 2021 – Present · 4 yrs 8 mos · Noida, Uttar Pradesh, India · On-site

Spearhead the development and optimization of emulation-based methodologies and workflows, with a focus on integrating generative AI techniques to enhance efficiency, scalability, and automation.
Drive innovation in emulation workflows to accelerate debug processes, enhance test coverage, and minimize turnaround time. Enable robust pre-silicon and post-silicon validation of complex SoC designs, with a specific focus on low-power and DFT (Design-for-Test) test cases.

EmulationGenerative AIDebuggingTest CoverageLow-Power TestingValidation

Synopsys inc

3 roles

R&D ENGINEER, STAFF

Jun 2019 – Jul 2021 · 2 yrs 1 mo

Develop hybrid solutions for SOC/IP verification by enabling design porting onto Virtualizer and ZeBu platforms. Ensure seamless integration of Virtualizer-based virtual prototypes with HAPS Series FPGA-based prototypes and ZeBu Series emulators to facilitate comprehensive and scalable verification workflows.

SOC/IP VerificationVirtualizationIntegrationVerification

Sr. R&D Engineer II

Jun 2016 – Jul 2021 · 5 yrs 1 mo

UFS Transactor – Architecture & Global Ownership
Designed and architected UFS2.0, UFS2.1, and UFS3.0 transactors for ZeBu-based emulation subsystems.
Global ownership of all customer deployments related to UFS transactors.
Led R&D initiatives for UFS transactor development and innovation worldwide.

UFS TransactorArchitectureGlobal OwnershipTransactor Development

Sr. Engineer R&D 1

Jul 2013 – May 2016 · 2 yrs 10 mos

Enhanced PCIe VIP test suite by developing the enumeration feature, improving protocol validation.
Developed and integrated memory models including DDRx/LPDDRx, NAND, and NOR Flash for ZeBu-based emulation platforms.

PCIe VIPMemory ModelsProtocol ValidationValidationIntegration

Freescale semiconductor

Lead Validation Engineer

Jul 2006 – Jun 2013 · 6 yrs 11 mos · noida

Post-Silicon & Pre-Silicon Validation Contributions
Designed a synthesizable FPGA-based VIP for AD9361 RF Transceiver, enabling post-silicon validation of Femtocell’s Antenna Interface Controller.
Led system-level post-silicon validation of key subsystems including DMA Controller, DDR Controller, and eSDHC Controller.
Developed a synthesizable Bus Functional Model (BFM) of SD Card for pre-silicon validation of the eSDHC Controller.
Built Freescale’s first full-chip emulation testbench on Palladium and RPP platforms, supporting early pre-silicon validation.

Post-Silicon ValidationPre-Silicon ValidationFPGAValidationDesign