Mohita Batra — Operations Associate
I’m a digital design engineer with 12+ years of experience in front-end ASIC development, currently managing and scaling a high-performing team at Synopsys. My career spans from deep hands-on design work to technical leadership across complex ASIC chips involving high-speed interface PHYs. My expertise includes: - RTL architecture and development - Synthesis, timing constraints (SDC), and timing closure - Formal verification, design checks, and handoff to PnR - Smart ECOs and RTL automation for accelerated turnaround I’m passionate about building not just high-quality chips, but resilient, forward-thinking teams that thrive in fast-paced, technically demanding environments.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC development and team leadership.
Location: Noida, Uttar Pradesh, India
Experience: 13 yrs 5 mos
Career Highlights
- Over 12 years of ASIC development experience.
- Expert in RTL architecture and timing closure.
- Proven track record in leading high-performing teams.
Work Experience
Synopsys Inc
Manager II, ASIC Digital Design (3 yrs 2 mos)
Manager I, ASIC Digital Design (2 yrs 7 mos)
ASIC Digital Design Engr, Sr II (6 mos)
ASIC Digital Design Engr, Sr I (2 yrs 1 mo)
ASIC Digital Design Engr, II (1 yr)
STMicroelectronics
Senior Design Engineer (3 yrs 8 mos)
Trainee (5 mos)
Ericsson
Intern (1 mo)
Education
BE at Manipal Institute of Technology
ISC Board at Seth M.R. Jaipuria School
ICSE Board at Seth M.R. Jaipuria School
