GOKUL MOHAN

Software Engineer

Bengaluru, Karnataka, India11 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in Memory Design and Static Timing Analysis.
Proven track record in leading complex IC design projects.
Strong foundation in VLSI from IIT Roorkee.

Stackforce AI infers this person is a Memory Design Engineer with expertise in VLSI and IC design.

Contact

Skills

Core Skills

Static Timing AnalysisMemory DesignTiming ClosurePower AnalysisCharacterizationMemory Compiler Implementation

Other Skills

Multiport RF memory designsPPAL optimisationEMIR closuresPoweron analysisESPCV Equivalence CheckEMIR for 5nm Register Files3nm Multiports8nm - One time programmablesTotem EM-IR reliability checksCrossfire validationPower and Leakage AnalysisBitcell characterizationERC checksPERC, ESD ChecksLibrary Generation

About

Memory Design Engineer | Aviation Enthusiast

Experience

11 yrs 11 mos

Total Experience

2 yrs 4 mos

Average Tenure

1 yr 7 mos

Current Experience

Qualcomm

Senior Lead Engineer

Sep 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India · On-site

Responsible for developing Multiport RF memory designs for the Nuvia Custom Cores
Static Timing analysis
PPAL optimisation
EMIR closures

Multiport RF memory designsStatic Timing analysisPPAL optimisationEMIR closuresStatic Timing AnalysisMemory Design

Broadcom inc.

IC design engineer

Feb 2021 – Sep 2024 · 3 yrs 7 mos · Bengaluru, Karnataka, India

Responsible for Poweron analysis, Timing closure, ESPCV Equivalence Check, EMIR for 5nm Register Files, 3nm Multiports, 8nm - One time programmables, Totem EM-IR reliability checks,

Poweron analysisTiming closureESPCV Equivalence CheckEMIR for 5nm Register Files3nm Multiports8nm - One time programmables+3

Stmicroelectronics

Memory Design Engineer

Sep 2019 – Feb 2021 · 1 yr 5 mos · Greater Noida

Started working as Memory Design Engineer in STMicroelectronics, Greater Noida in deputation from Zia Semiconductors Pvt Ltd
Crossfire validation on 28nm SOI compilers,
Power and Leakage Analysis.
Bitcell characterization with Ion, Ioff, SNM, WM calculation.
ERC checks on 28nmSOI compilers.
PERC, ESD Checks on 28nmSOI compilers
Library Generation
Impact Analysis and verification
AVM implementation
LVF implementation
Characterization of Decoupling Capacitance and it's validations.
Grid Validations
Impact Analysis due to change in spice, simulator and a design change
Development of Automation scripts
Crossfire Validation on entire platform

Crossfire validationPower and Leakage AnalysisBitcell characterizationERC checksPERC, ESD ChecksLibrary Generation+7

Zia semiconductor pvt ltd

Design Engineer I

Oct 2018 – Feb 2021 · 2 yrs 4 mos · Bengaluru Area, India

As part of Internal project
Implementation of C40_SRAM compiler.
Bitcell Characterization. Calculation of SNM, WM,Ion, Ioff
Sense Amplifier Characterization
Static Timing Analysis - Calculated setup timing, hold timings, setup hold slack and cycle times.
Marginality checks and fix.
Tight stimuli implementation
Power and Leakage Analysis
Critical path Modelling of C40_SRAM compiler
Shell ,pearl scripting
DRC of 14nm, 90nm technology
Layout Versus Schematic (LVS) checks

Implementation of C40_SRAM compilerBitcell CharacterizationStatic Timing AnalysisMarginality checksPower and Leakage AnalysisCritical path Modelling+4