Dipesh V. — Product Engineer
A Digital Design Verification enthusiast, having an inclination for Development of Verification Architecture. *Frontend:* Verilog System Verilog UVM Experience in Verification Architecture Developement from scratch. *Backend:* Hands on Partitioning ,Floorplanning & PnR Implementation Tool : Inovus Tech Node : 5nm , 4nm Protocols: I2C, ASI, I2S , MIPI Soundwire. PS : I am not a Full stack Chip Designer https://alumni.mnnit.ac.in/profile/140516569218649101
Stackforce AI infers this person is a Digital Design Verification Engineer specializing in advanced semiconductor technologies.
Location: Bengaluru, Karnataka, India
Experience: 4 yrs 8 mos
Skills
- Wireless Technologies
- Ieee 802.11
- Systemverilog
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in Digital Design Verification and Architecture Development.
- Proficient in SystemVerilog and UVM methodologies.
- Experience with advanced tech nodes like 5nm and 4nm.
Work Experience
Qualcomm
Design Verification Engineer (1 yr 10 mos)
Interim Engineering Intern (11 mos)
Texas Instruments
Digital Verification Engineer (1 yr 11 mos)
Education
MTech at Motilal Nehru National Institute Of Technology
Bachelor of Technology - BTech at Government College of Engineering, Amravati.
at Kendriya Vidyalaya
