Oct 2024 – Present · 1 yr 6 mos · Bengaluru · On-site

• Developing and optimizing EDA synthesis tool features using Verilog, C/C++ and Bash, with debugging using GDB.
• Designed and implemented verification methodologies and automated flows to identify and resolve timing, functional, and resource issues across advanced IP blocks.
• Built unit tests and testbenches (GoogleTest, Verilog) to ensure robust functional coverage and tool stability for major semiconductor customers.
• Collaborated with global customers ( Nvidia, AMD, Apple, Google, ARM, Qualcomm, Broadcomm, SpaceEx, Tesla, Intel) and cross-functional teams to gather requirements, debug issues, and deliver feature enhancements and fixes.
• Coordinated feature development and issue resolution across engineering, QA, Product managers and customer teams, ensuring timely delivery of releases. ( Program Management and Product Management Exposure)

Mar 2022 – Sep 2024 · 2 yrs 6 mos

Jun 2019 – Mar 2022 · 2 yrs 9 mos · Hyderabad

• Application Design and Development and Frontend Verification of C/C++ features based on Vitis Software
• Created following applications based on FPGA -
• i. Stock analysis application with financial advisory and portfolio analysis report for investors (Fintech)
• ii . Model for Carbon dioxide emissions reduction to slow and reverse global warming.
• (Climate Change)
• Validated AIE and PL kernels for Vitis Software using C++/C Linux based programming and Verilog.
• i. Float support ii. Templatization iii. Restrict Keyword iv. Global Variables support v. Inline function support
• Internal features verification
• Throughput, latency, reports analysis, loop unrolling and pipelining, constraints check, heap and stack size requirements.

Jan 2019 – Jun 2019 · 5 mos · Bengaluru, Karnataka, India

• Worked as member of PCIe Physical layer Design team
• Developed an overall understanding of PCIe protocol with detailed analysis of physical layer.
• Was involved in developing Perl scripts and removing Spyglass waivers.
• Wrote Verilog code for various sub blocks of transmit lane of PCIe to convert it from 2 symbol mode to 4 symbol mode for Gen 5 and to 8 symbol mode for Gen6.
• 1. Fixed the Data Scrambler perl code and made it work from 2 symbol mode to 4 symbol mode for Gen5 .
• 2. Converted data width from 16 bits to 32 bits in 128b/130b Sync header Shifter.
• 3. Worked on RTL coding for conversion of Training sets coming from LTSSM , from 2 symbol mode to 4 symbol mode in 128b/130b Sequence generator of Transmit Lane Block
• Gave more than 10 presentations to team on topics like PCIe protocol understanding, research paper on Clock domain Crossing Design and verification techniques and non-blocking assignments Coding Styles in Verilog Synthesis.

May 2017 – Jul 2017 · 2 mos · Mumbai, Maharashtra, India

• Review of Siemens ME Teleperm Distributed Control System used in power plant.
• Analyzed description of its hardware, software, data bus system and process parameter both in control room and on field inspection of process controlled in power plant.
• Worked as part of team in implementation of this system in Boiler drum level control measurement.

Dec 2016 – Feb 2017 · 2 mos · Chennai, Tamil Nadu, India

• Was involved in building user interfaces for web applications and designing and developing responsive design websites.
• Managed online marketing campaigns and facilitated in promotion and installation of mobile applications to targeted customers.

Apr 2015 – Dec 2015 · 8 mos · Ahmedabad, Gujarat, India

• Communicated with over 150 individuals to collect reviews of college and presented survey based on information obtained.