Dhiraj Goswami

CEO

Wilsonville, Oregon, United States28 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Proven track record in hardware and software co-verification.
Expert in leading cross-functional teams across multiple geographies.
Innovator in algorithms and heuristics for complex problems.

Stackforce AI infers this person is a leader in hardware and software co-verification within the semiconductor industry.

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Skills

Core Skills

Hardware And Software ArchitectureMachine LearningSoftware DevelopmentTeam ManagementAutomatic Test GenerationAtpg ToolsDesign AutomationGeneralized Fault Model

Other Skills

AlgorithmsHeuristicsConstraint solvingSoftware synthesisHardware synthesisLow power designStatistical analysisAnalytical formulationPrototypingEmulationSimulationComplex software systemsSoftware releasesTest patternsTiming exceptions

About

Industry leader in all aspects of HW and SW co-verification with a predictable delivery track record. Always demonstrated technical innovation and operational excellence along with building a great team spanning across multiple geographies. Specialties: Hardware and software architecture for complex system, algorithms and heuristics for hard problems, constraint solving, software and hardware synthesis, low power, problem partitioning, statistical analysis, analytical formulation, prototyping, emulation, simulation, machine learning.

Experience

28 yrs 10 mos

Total Experience

5 yrs 9 mos

Average Tenure

7 yrs 8 mos

Current Experience

Cadence design systems

CVP & GM, HSV

Aug 2018 – Present · 7 yrs 8 mos · Portland, Oregon Metropolitan Area

Corporate Vice President and General Manager , Head of HSV (Palladium, Protium, Helium, Solutions and HW Cloud3.0): July, 2021 to Present
Vice President Research & Development, Head of Emulation, Prototyping, Hybrid and Virtual Platform: November, 2019 to June, 2021
Vice President Research & Development, Head of ML and Emerging Technology: August, 2018 to November, 2019

Hardware and software architectureAlgorithmsHeuristicsConstraint solvingSoftware synthesisHardware synthesis+7

Synopsys

Fellow, R&D Technology & Operational Leader, R&D Head of ZeBu Software Development

Apr 2007 – Aug 2018 · 11 yrs 4 mos · Portland, Oregon Metropolitan Area

As R&D head of ZeBu Emulation Software Development, managed a large team across different geographical locations in the US, Europe, India and China. The team involved in developing complex software systems and managed ZeBu software releases.

Software developmentTeam managementComplex software systemsSoftware releases

Mentor graphics

Research Staff Engineer

Sep 2003 – Mar 2007 · 3 yrs 6 mos

Invented and managed the implementation of an efficient automatic test generation solution to generate accurate test patterns with the highest quality in the presence of timing exceptions and constraints. This has become foundation for all the commercial ATPG tools in the market including FastScan and TestKompress.

Automatic test generationTest patternsTiming exceptionsATPG tools

Intel

Manager, Design Automation Flow

Dec 1999 – Sep 2003 · 3 yrs 9 mos

I built a core group of engineers, and enabled them to develop and support design flows for logic synthesis, place and route, physical verification, design-for-test, and design-for-manufacturability. These design flows were used for successful tap-outs of chips in PDA and cell phone market. I invented Generalized Fault Model (GFM) to represent various defects in nanometer silicon technology and the faults arising due to circuit and process marginalities. I architected and led the implementation of a sequential ATPG tool based on GFM. The complexities included handling of partial scan designs, various scan design styles, clock gating, and high capacity for microprocessor designs.

Design automationLogic synthesisPhysical verificationDesign-for-testDesign-for-manufacturabilityGeneralized Fault Model+1