Jul 2018 – Present · 7 yrs 10 mos · Israel

• Led PHY-level electrical validation of high-speed TX/RX analog circuits for USB4, PCIe Gen5,
• DP2.1, and DDR5 memory subsystems across multiple generations (10th-16th).
• Drove pre-silicon validation ramp including design and schematic reviews, silicon readiness alignment, validation coverage definition, and risk assessment.
• Defined first-silicon validation strategy including PVT coverage, compliance readiness, and stress characterization planning.
• Prepared lab infrastructure, equipment and automation frameworks, including measurement setups, stress, compliance tooling, and data acquisition flows.
• Led structured silicon bring-up, full PHY validation, and complex electrical debugging from first power-on through production release.
• Executed extensive validation plans covering functionality, electrical characterization, compliance testing, signal integrity analysis, jitter decomposition, and PVT margining.
• Performed high-speed electrical characterization using oscilloscope, BER, DC power analyzer, VNA, and precision instrumentation to analyze eye integrity, jitter components (RJ/DJ/ISI), BER behavior, and voltage/temperature margins across operating corners.
• Documented and tracked PHY validation issues through bug-tracking system, including failure reproduction, waveform evidence, root-cause analysis, and fix verification.
• Analyzed schematic sections of high-speed PHY interfaces to trace signal paths and accelerate electrical failure isolation.
• Developed Python-based automated validation flows and script-driven test flows to improve coverage, repeatability, and lab efficiency.
• Led cross-functional debugging of complex PHY-related issues with design, firmware, system, and HVM teams, driving structured root-cause analysis through silicon-level fixes and production issue resolution.
• Partnered with HVM team to explore innovation for test time reduction and coverage.
• Co-lead of global Memory I/O Guild, responsible for standardization and methodologies.