Sanjeeb Mishra — Associate Partner
Accomplished and results-driven Semicon professional with over 25 years of experience in ASIC (DFT/SOC-Engineering/Validation/Automotive Quality ) and product development in multinational environments. Expertise in DFT (DFT/DFX Architect/TestEng/Scan/ATPG), end-to-end SOC design flow, pre/post/VP validation & verification, characterization, and board and firmware development, involving protocols like eMMC, SD, USB3.2, DSI, CSI, DDR4, I3C, ONFI-TM, PCIe4, NVMe, SAS4, and SATA. Combines technical acumen with management skills to ensure successful product deliveries and market wins. Technical Leadership and Management: Proven leader in managing complex SOC deliveries, covering all DFT aspects, pre/post validation, characterization, and productization, with effective team management. Broad Industry Exposure: Extensive knowledge across the semiconductor industry, including storage (SSD, eSSD, retail), servers, clients, mobile, displays, and telecom. Expertise in ASIC management, DFT, pre-silicon validation (Palladium/HAPS/FPGA/VPs), post-silicon validation, characterization, packaging (2.5/3D), and reference design (boards and turnkey). DFT_DFX Expertise: Proficient in architecting JTAG/iJTAG-based infrastructure with OCC insertion, BSCAN, SCAN, compression, instrumentation, MBIST, ATPG, GLS simulation, and debugging ATE patterns and PDL preamble. Validation and Verification Expertise: Skilled in pre/post-silicon validation and verification using System-C VPs, FPGA, Protium, Palladium, HAPS, and tools like Git, Linux, and GCC. Specializes in automation frameworks for instrument/test automation. Protocol and IP Knowledge: Extensive understanding of IP and system architecture, SOC architecture, and protocols such as OpenCAPI, CXL, SDe7, DDR3/4, LPDDR, I3C, DSI-CSI, MIPI-Slimbus, ONFI, PCIe4, NVMe, SAS, QSPI, I2C, SMbus, JTAG. Expertise includes CPUs and analog hard IPs. Mentorship and Collaboration: Skilled in providing tactical leadership through mentorship, fostering a collaborative work environment ।
Stackforce AI infers this person is a Semiconductor Validation Architect with extensive experience in SOC design and validation.
Location: Bengaluru, Karnataka, India
Experience: 25 yrs 10 mos
Skills
- Dft
- Soc Flow
- Validation Management
- Engineering Management
- Validation Architecture
- Embedded Hardware Development
Career Highlights
- Over 25 years of experience in semiconductor industry.
- Expertise in DFT and SOC design flow.
- Proven leadership in managing complex SOC deliveries.
Work Experience
L&T Semiconductor Technologies
Associate Director ( R&D ) (1 yr 5 mos)
Western Digital
_ (1 mo)
Senior Manager, ASIC Development Engineering, (4 yrs 5 mos)
Microchip Technology Inc.
Senior Manager (3 yrs 5 mos)
Intel Corporation
Validation Architect (4 yrs 11 mos)
STMicroelectronics
Specialist (9 yrs)
M/s Himachal Futuristic Communications Limited
Asst Manager ( R& D) (2 yrs 1 mo)
Webel Mediatronics
Development engineer (1 yr 8 mos)
National Physical Laboratory (NPL)
Intership (0 mo)
Education
Master's degree at Institute of Radio Physics and Electronics
BTech at University of Calcutta
PG Level Advanced Certification Programme in VLSI Chip Design at Indian Institute of Science (IISc)
