Gopal Chandnani

Software Engineer

Bengaluru, Karnataka, India9 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in semiconductors industry.
  • Proficient in Universal Verification Methodology.
  • Strong background in Electrical and Electronics Engineering.
Stackforce AI infers this person is a semiconductor verification engineer with strong technical skills in UVM and SystemVerilog.

Contact

Skills

Other Skills

Universal Verification Methodology (UVM)Microsoft ExcelSystemVerilogC (Programming Language)C++

About

Experienced Project Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), Microsoft Excel, SystemVerilog, C (Programming Language), and C++. Strong information technology professional with a Bachelor's degree focused in Electrical, Electronics and Communications Engineering from Ahmedabad Institute Of Technology.

Experience

9 yrs 3 mos
Total Experience
2 yrs 3 mos
Average Tenure
5 yrs 5 mos
Current Experience

Mediatek

2 roles

Staff Engineer

Jun 2023Present · 2 yrs 10 mos

Senior Verification Engineer

Oct 2020May 2023 · 2 yrs 7 mos

Synapse design inc.

2 roles

Senior Design Verification Engineer

Promoted

Apr 2019Oct 2020 · 1 yr 6 mos

Verification Project Engineer

Nov 2017Mar 2019 · 1 yr 4 mos

Aceic design technologies

Verification Project Engineer

Apr 2017Oct 2017 · 6 mos · Bengaluru, Karnataka, India

Adaptive technology (i) pvt ltd.

PCB Designer

Jul 2016Jan 2017 · 6 mos · Gujarat, India

Education

Ahmedabad Institute Of Technology

Bachelor's degree

Jan 2013Jan 2017

V.P.M.P. Polytechnic, Gandhinagar 654

Diploma

Jan 2010Jan 2013

GLS MK Secondary and Higher Secondary School

Secondary Education

Jan 2008Jan 2010

Tripada Day School

Primary education

Jan 1997Jan 2008

Stackforce found 100+ more professionals with Universal Verification Methodology (UVM) & Microsoft Excel

Explore similar profiles based on matching skills and experience