md akramuddin

Software Engineer

Hyderabad, Telangana, India11 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 10 years of experience in FPGA and ASIC design.
  • Expertise in Networking stack protocols and encryption algorithms.
  • Proficient in multiple FPGA implementation tools.
Stackforce AI infers this person is a highly skilled FPGA and ASIC design engineer with extensive experience in networking and validation.

Contact

Skills

Core Skills

CommunicationPython (programming Language)FpgaAsicNetworkingSd Protocol

Other Skills

Trace32LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)VeloceStatic Timing AnalysisDebuggingApplication-Specific Integrated Circuits (ASIC)RTL DesignFPGA prototypingEmulationSilicon ValidationXilinx ISETCL

About

Member of Technical staff with over 10 years of experience in Emulation, FPGA Design, FPGA prototyping, Pre/Post Silicon Validation, front end RTL design, Microarchitecture, IP integration, On-Chip debugging, development and verification for target FPGA and ASIC. Experience in implementation of Networking stack protocols UDP, Encryption (AES) algorithms, Signal Processing Algorithms ,and SDHOST controller using Verilog HDL on FPGAs. Proficient in TCL, Shell scripting languages Worked on VGA, I2C, SPI , Tri-mode (10/100/1000) Ethernet, PCIe Gen 3 in End point mode. Experience in AXI4 , XGMAC,SDHOST, XGMII,GMII,RGMII, Xilinx 10GBASE-R PCS/PMA protocols, MIPS and RISC processor Worked on Emulation tool Veloce, Good hands on experience in using FPGA implementation tools like Xilinx ISE, Vivado, Libero, Vivado IP integrator, Chip scope pro, Vivado Logic analyzer. hands on experience in handling Xilinx Vertex 7 boards viz. VC707 Evaluation Board, VU19P, Zed board, Spartan 3A, Spartan 3E, ICICLE kit, Polarfire, Polarfire SoC

Experience

11 yrs 10 mos
Total Experience
2 yrs 4 mos
Average Tenure
4 yrs 3 mos
Current Experience

Amd

2 roles

Member of Technical Staff

Jul 2024Present · 1 yr 10 mos · Hyderabad, Telangana, India

CommunicationTrace32Python (Programming Language)

Senior Silicon Design Engineer

Feb 2022Jul 2024 · 2 yrs 5 mos · Hyderabad, Telangana, India

LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)VeloceCommunication+9

Xilinx

Senior Engineer

May 2021Feb 2022 · 9 mos · Hyderabad, Telangana, India

LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)VeloceCommunication+9

Microchip technology inc.

Senior Engineer-II

Feb 2021May 2021 · 3 mos · India

LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)CommunicationStatic Timing Analysis+8

Microsemi corporation

Senior Engineer, Systems Validation

Apr 2018Feb 2021 · 2 yrs 10 mos · Hyderabad, Telangana, India

LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)CommunicationStatic Timing Analysis+8

Centre for development of advance computing, hyderabad (c-dac)

Project Engineer

Apr 2015Apr 2018 · 3 yrs · Hyderabad Area, India

  • worked on Networking protocols TCP/UDP, implemented UDP TX and RX . Also interface opensource XGEMAC , 10GBASE-R IP CORE from xilinx with UDP Transmitter and interfaced with vc707.
  • Also worked on SD protocol, implemented command control logic in SDHOST controller IP core design
LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)CommunicationStatic Timing Analysis+5

Cdac

Project Associate

Apr 2014Apr 2015 · 1 yr · Ameerpet ,hyderabad

LinuxRTL CodingField-Programmable Gate Arrays (FPGA)Very-Large-Scale Integration (VLSI)CommunicationStatic Timing Analysis+5

Education

Muffakham Jah College Of Engineering And Technology

Master of Engineering (M.Eng.) — DIGITAL SYSTEMS

Jan 2011Jan 2013

Muffakham Jah College Of Engineering And Technology

B.E — E.C.E

Jan 2007Jan 2011

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