Prakash Gudala

Software Engineer

Hyderabad, Telangana, India12 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

8+ years in RTL Design for hardware solutions
Expertise in FPGA and ASIC design and validation
Strong background in cloud computing acceleration

Stackforce AI infers this person is a Hardware Design Engineer specializing in FPGA and ASIC solutions for cloud computing and AI applications.

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Skills

Core Skills

Rtl DesignFpgaFunctional Verification

Other Skills

Field-Programmable Gate Arrays (FPGA)FPGA based SOC designSystem VerilogVerilogDebuggingEmulationCFPGA prototypingDPIValidationStatic Timing AnalysisRTL CodingLogic SynthesisApplication-Specific Integrated Circuits (ASIC)Timing Closure

About

8+ years of experience in RTL Design for Hardware Accelerator/ASIC/FPGA solutions and basic Functional Verification, Synthesis, SoC design/integration, FPGA Smart Design/ debugging and validation on hardware, with domain expertise in Hardware accelerators implementation for Cloud (big data analytics)/AI/Image processing/CV solutions and system-level validation and debug of system solutions. As a Senior Engineer, my responsibilities are RTL development and verification and IP/System-level validation.

Experience

12 yrs 5 mos

Total Experience

3 yrs 1 mo

Average Tenure

4 yrs 1 mo

Current Experience

Intel corporation

Sr. Hardware Design engineer

Mar 2022 – Present · 4 yrs 1 mo · Hyderabad, Telangana, India

I am working as Sr. Hardware Engineer in cloud computing acceleration group. My responsibilities are RTL design, FPGA system design, basic module level test bench verification(including coverage) and validation on the real FPGA setup.

RTL DesignField-Programmable Gate Arrays (FPGA)FPGA

Microchip technology inc.

Senior Engineer - 2 (Design)

Nov 2019 – Feb 2022 · 2 yrs 3 mos · Hyderabad, Telangana, India

I worked as a Senior Engineer (RTL Design and Validation and Verification for both FPGA and ASIC) in Microchip India Pvt.Ltd

Manjeera digital system pvt.ltd

RTL Design and Verification Engineeer

Jan 2015 – Nov 2019 · 4 yrs 10 mos · Greater Hyderabad Area

My main activities/experience focuses on RTL Design, Functional Verification, FPGA based SOC design, and Writing test bench to check the RTL by using System Verilog and Verification on FPGA in real time(emulation) by using SDK.

RTL DesignFunctional VerificationFPGA based SOC designSystem Verilog