Shivangi Tripathi

Product Manager

Bengaluru, Karnataka, India8 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in RISC-V CPU Design and RTL Implementation.
Strong background in Digital Design methodologies.
Proven track record in micro-architecture and synthesis.

Stackforce AI infers this person is a Digital Design Engineer specializing in RISC-V architecture and RTL design.

Contact

Skills

Core Skills

Risc-vRtl Design

Other Skills

Micro-architectureVerilogPPASTASynthesisTiming ClosureSystem-VerilogMicrocontrollers (Atmega, Arduino)Verilog VHDLMicrosoft OfficeCustomer ServiceMicrosoft ExcelManagementMicrosoft WordPowerPoint

About

I'm currently working on RISC V CPU Design as RTL Design Engineer. Over the years, I have developed skills essential to Digital Design which includes Micro-architecture, RTL Design Implementation, PPA, Synthesis, STA, Lint/ CDC for ASIC and FPGAs.

Experience

8 yrs 3 mos

Total Experience

2 yrs 1 mo

Average Tenure

1 yr 11 mos

Current Experience

Qualcomm

Senior Lead Engineer

May 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

CPU Design at Qualcomm (Nuvia)

RISC-VMicro-architectureRTL DesignVerilogPPASTA+2

Mips

Senior Design Engineer

Nov 2022 – Apr 2024 · 1 yr 5 mos · Bengaluru, Karnataka, India

Working on Design and Implementation of Trace Unit in RISC-V Core.

RISC-VRTL Design

Intel corporation

IP Design Engineer

Jul 2019 – Nov 2022 · 3 yrs 4 mos · Bangalore

Worked on coherent Interconnect for Server, got basic exposure to coherency protocols proprietary to Intel.
Responsible for micro-architecture, RTL Design Implementation, Synthesis, Timing closure, PPA, Lint, CDC, STA, Debug support to verification team.

STAVerilogRTL Design

Logic-fruit technologies

R & D Engineer

Nov 2017 – Jun 2019 · 1 yr 7 mos · Gurugram, Haryana, India

Worked on RTL Design and Implementation of GenZ Jammer using PCIe PHY Gen4, X16, ARINC 818 protocol, DisplayPort PHY layer protocol.

RTL DesignMicro-architecture

Mentor graphics

Intern

Jun 2016 – Jul 2016 · 1 mo · Noida, Uttar Pradesh, India

HEP training on Verilog and System-Verilog
I have got hand-on experience on QUESTA-SIM , verification tool developed by MENTOR GRAPHICS. This was an extensive 2 months training in which all the concepts related to Verilog , System-Verilog , Random test case generation, Assertions , Basic UVM were made clear. I also designed and verified functionality of LC-3 MICROCONTROLLER.

RTL Design