Jul 2023 – Mar 2025 · 1 yr 8 mos · India · Hybrid

• Working on PCIe and CXl protocol:
• 1. Debugged and resolved test case failures for CXL 2.0, CXL 3.0, PCIe Gen5, and Gen6 protocols across various project milestones.
• 2. Identified and resolved critical issues in protocol debugging, ensuring compliance with CXL and PCIe standards.
• 3. Analyzed and improved functional coverage by identifying low bin hit counts, understanding root causes, and adding scenarios to achieve expected bin coverage.
• 4. Contributed significantly to verification efforts, driving successful milestone achievements and ensuring high-quality deliverables.

Feb 2022 – Jun 2023 · 1 yr 4 mos · Bengaluru, Karnataka, India

• Working on the PCI Express
• 1. Development of software for Packet generator including LCRC and ECRC at datalink layer and
• transaction layer, Frame structure for Transaction Layer Packet (TLP) and Data Link Layer Packet for all the versions till PCIe gen 5 for various configurations to emulate the Analyzer environment.
• 2. Driving the generated packets to DUT via driver to verify the design.
• Working on the CXL (CXL.IO)
• The integration of the testbench with the DUT, as well as the incorporation of debug signals and functions, enables verification of the design through the execution of various test cases.
• Working on PCIe - Retimer
• 1. Deep-dive analysis of the BFM model, to understand the VIP design and its adaptations for custom specification.
• 2. Performing a series of PCI Express (PCIe) test cases to verify the functionality of the retimer device under test (DUT).
• 3. Developing testbenches for the APB (Advanced Peripheral Bus) and WB (Wishbone) protocols.

May 2021 – Jan 2022 · 8 mos · India

• Working on RISC-V based SoC IP design
• 1. Build SoC design using open source IP's (opentitan)
• 2. Customization of IP's as per the design requirements (Python scripts)
• 3. Test software development to evaluate customized IP's (C-language)
• 4. Develop python scripts to run the regression over the design
• 5. Replacing software dpi's to synthesizable rtl modules to interact with SoC
• 6. Design simulation in xcelium platform

Oct 2019 – Dec 2019 · 2 mos · Bangalore Urban, Karnataka, India

• Design and verify blocks in the transmission pipeline for optical communication as per CCSDS standard.
• 1. FPGA design for basic blocks like pseudo-randomizer, cyclic redundancy check, convolutional encoder and pulse position modulator.
• 2. FIFO design for data buffering.
• 3. MATLAB scripts for data generation and correlation.

Jul 2018 – Mar 2019 · 8 mos · Bangalore Urban, Karnataka, India