Midhun K Dinesh

Product Engineer

Bengaluru, Karnataka, India12 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT automation and IP validation.
Proven leadership in managing cross-functional teams.
Strong background in EDA tools and hardware design.

Stackforce AI infers this person is a Semiconductor Engineering Specialist with a focus on EDA tools and automation.

Contact

Skills

Core Skills

Dft AutomationIp ValidationEda Tool DevelopmentHardware Design

Other Skills

Design-for-Test (DFT) IP integrationTessent-based tool workflowsMemory BIST (MBIST) integration flowsIP validation automationCommunicationCross-functional Team LeadershipScriptingPerlAutomationtessentVerilogSystemVerilogUnix Shell ScriptingVLSILinux

About

EDA Tools Hardware Engineering Manager at Intel Corporation, Bengaluru. Leads and manages a dedicated team focused on automation, specializing in areas like Design-for-Test (DFT) IP integration, Tessent-based tool workflows, Memory BIST (MBIST) integration flows, and IP validation automation. Drives efficiency and innovation in testing processes to deliver robust and scalable solutions.

Experience

12 yrs 8 mos

Total Experience

4 yrs 2 mos

Average Tenure

9 yrs 11 mos

Current Experience

Intel corporation

6 roles

Sr. EDA Tools Hardware Engineer

Aug 2025 – Present · 8 mos

EDA Tools Hardware Engineering Manager

Promoted

Dec 2024 – Present · 1 yr 4 mos

Leads and manages a dedicated team focused on automation, specializing in areas like Design-for-Test (DFT) IP integration, Tessent-based tool workflows, Memory BIST (MBIST) flows, and IP validation automation. Drives efficiency and innovation in testing processes to deliver robust and scalable solutions.

Design-for-Test (DFT) IP integrationTessent-based tool workflowsMemory BIST (MBIST) integration flowsIP validation automationDFT AutomationIP Validation

Sr. EDA Tools Hardware Engineer

Promoted

Oct 2023 – Dec 2024 · 1 yr 2 mos

Designs, implements, verifies, and supports the enablement and adoption of hardware design tools, flows, and methodologies. Defines methodologies for hardware development related to technology node and EDA tool enabling. Creates and verifies unique hardware designs, assembles design platforms, and integrates components into hierarchical systems to provide deployment coverage for end-to-end EDA tool testing on new technology nodes. Develops, tests, and analyzes engineering design automation tools, flow, and methodologies to improve efficiency and optimize power and performance. Supports development and enhancement of platforms, databases, scripts, and tools flows for design automation. Builds deep understanding of digital design, verification, structural and physical layout, full-chip integration, power and performance, clocking, and/or timing to enhance future TFM development. Collaborates with EDA vendors on defining and early testing of next-generation design tools.

CommunicationCross-functional Team LeadershipEDA Tool DevelopmentHardware Design

Sr DFT Automation Engineer

Mar 2020 – Nov 2023 · 3 yrs 8 mos

DFT Automation Engineer. Working on Siemens Tessent-based DFT integration automation solutions. Worked on Validation using Mentor ICL/PDL methodology.
Developed one-touch Perl SG-CDC Automation Flow for SoC integration and IP regression usage.
Cross-site POC for in-house DFT IP integration/RTL+collaterals autogeneration tool.
Managed Shared Engineering activities including Git/Gatekeeper/Disk management etc across the sites for the full team.

ScriptingDFT Automation

DFT TFM Engineer

Aug 2016 – Mar 2020 · 3 yrs 7 mos

IP/subsystem Integration and automation.
Created FE subsystem integration automation suite using in-house integration tools. Sub-system integration experience in SoC Team.
Compute and other miscellaneous management responsibilities across sites in the team.

Graduate Technical Intern

Mar 2016 – Jun 2016 · 3 mos · Bengaluru Area, India

1) Formal verification using JasperGold
2) Design Automation
3) TFM
4) DFT

Intel labs

Graduate Technical Intern

Jul 2015 – Feb 2016 · 7 mos · Bengaluru Area, India

1) Design of Memory Controller IP and FPGA testing.
2) Fabric and Peripheral Verification using C based tests corresponding to UVM tests.

Cognizant

2 roles

Programmer Analyst

Promoted

May 2013 – Jul 2014 · 1 yr 2 mos

Support and development activities in Datawarehousing Domain. Developed and maintained projects in Datastage 8.1, 8.7 in Unix and Linux environments. Worked in Oracle and Vertica Databases for two years. Interests in creation and maintenance of Unix shell scripts. Received onsite and offshore appreciations for performance.