Ashutosh Singh

DevOps Engineer

India4 yrs experience

Highly Stable

Key Highlights

Expert in SoC validation and high-speed interface technologies.
Proficient in MATLAB and Python for automation and validation.
Strong collaboration skills with cross-functional teams.

Stackforce AI infers this person is a High-Tech Validation Engineer specializing in SoC and high-speed interface technologies.

Contact

Skills

Core Skills

Soc ValidationIp ValidationHigh-speed Interface ValidationSilicon Bring-upPost-silicon ValidationAutomated Testing

Other Skills

Thunderbolt IP ValidationUSB4 ValidationPCIeMATLABInterface DebugPythonC (Programming Language)VerilogSchematicDigital ElectronicsC++SerDesScriptingSimulation SoftwareProblem Solving

About

Currently employed as SoC Functional Validation Engineer @Intel | Validation of thunderbolt IP TBT4/USB4 as a discrete and integrated solution on SoCs - Panther Lake and Nova Lake. Previously worked at @Synopsys as senior research and development engineer | Post-Silicon Validation of High-Speed Interface PHY/IPs (Primarily PCIe) | Experienced in Silicon Bring-Up, Interface Debug and SoC-Level Validation Using SDK | Skilled in System-Level Debug Languages :- C, MATLAB Programming and Python Software/IDE :- Mathworks, VS Code, Vivado ISE Tools :- JTAG, Oscilloscope, Multimeter, Clock Generator, Variable ISI, Power Supplies, BERT Protocols :- PCIe, TBT4/USB4 Project Management :- JIRA, Confluence, MS Office, Perforce

Experience

4 yrs

Total Experience

3 yrs 7 mos

Average Tenure

5 mos

Current Experience

Intel corporation

SoC Functional Validation Engineer

Nov 2025 – Present · 5 mos · Bengaluru

Validation of Thunderbolt IP TBT4/USB4 as a discrete and integrated solution on SoCs - Panther Lake and Nova Lake

Thunderbolt IP ValidationUSB4 ValidationSoC ValidationIP Validation

Synopsys inc

3 roles

Senior Research And Development Engineer

Promoted

Jan 2024 – Nov 2025 · 1 yr 10 mos

Validation, designing and development of High-Speed Interface PCIe PHY-IP solutions. Bring-up of silicon (standalone IPs) on Evaluation Board in Lab. SDK based IP Validation through SoC environment simulation. Implements I2C clock module for PCIe IPs. Customer-debugs to identify and resolve IP-related issues during integration and validation. Collaboration with design, firmware and software teams to root cause issues and validate fixes.

PCIeMATLABHigh-Speed Interface ValidationSilicon Bring-UpInterface Debug

Research And Development Engineer

Mar 2022 – Dec 2023 · 1 yr 9 mos

Developed and validated High-Speed Interface PHY IPs. Contributed to creating MATLAB-based IP Validation tools for efficient PHY validation and automated testing. Designed and developed MATLAB and Python scripts to automate post-silicon validation, enabling faster execution, data analysis and regression testing of SerDes IPs.

PCIeMATLABPythonPost-Silicon ValidationAutomated Testing

Graduate Engineer Trainee

Nov 2021 – Feb 2022 · 3 mos

Developed an automation packaging tool for SerDes solutions to streamline the creation of executables for IP Validation software. This tool reduced manual intervention in the validation process, improving efficiency and accelerating the release cycles for High-Speed PHY IPs.

MATLABPython