Navin Garg

Engineering Manager

Bengaluru, Karnataka, India26 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in SoC and ASIC design methodologies.
  • Proven track record in reducing chip design turnaround time.
  • Extensive experience in customer support for VLSI tools.
Stackforce AI infers this person is a VLSI design expert with strong capabilities in SoC and ASIC development.

Contact

Skills

Core Skills

SocAsicVlsiSpyglassConformal SuiteLow Power VerificationLow-power

Other Skills

SemiconductorsEDAStatic Timing AnalysisMixed SignalRTL designTiming ClosurePhysical DesignFunctional VerificationTCLSystemVerilogDebuggingICFormal VerificationIntegrated Circuits (IC)Application-Specific Integrated Circuits (ASIC)

Experience

26 yrs
Total Experience
5 yrs 2 mos
Average Tenure
8 yrs 1 mo
Current Experience

Intel corporation

Engineering Manager

Mar 2018Present · 8 yrs 1 mo · Bengaluru, Karnataka, India

  • Tools, flows and methodology team, help reducing turn around time for chip design with quality.
  • Front end flows for SoC development execution
  • Infrastructure and flows for software development
SoCSemiconductorsEDAStatic Timing AnalysisASICMixed Signal+12

Synopsys inc

Application Consultant

Nov 2016Mar 2018 · 1 yr 4 mos · Noida, Uttar Pradesh, India

  • Field Application Engineer, work with large VLSI design houses as their last line of support for any critical issues of SpyGlass, VCS and VC-LP tools.
  • Provide pre/post sales technical support to customers.
VLSISpyGlassVCSVC-LP

Cadence design systems

Principal Application Engineer

Mar 2011Nov 2016 · 5 yrs 8 mos · Noida, Uttar Pradesh, India

  • Principal Application Engineer in Front End Design Team, provide post sales support for Conformal suite (Logical Equivalence Checking, Low power verification, ECO), Encounter Digital Implementation, Innovus
  • Provide custom solutions which ease the tool adoption for the customer.
  • Supporting the sales team in technical product presentation and demonstration.
  • Handle key accounts and help in tool evolution meeting customer expectations.
  • As Knowledge team member responsible for creating/reviewing/publishing self-help articles on Cadence Online Support.
  • Deliver presentation and trainings to the customers.
Conformal suiteLogical Equivalence CheckingLow power verificationECOEncounter Digital ImplementationInnovus

Atrenta

Senior Consulting Applications Engineer

Nov 2005Mar 2011 · 5 yrs 4 mos · Noida, Uttar Pradesh, India

  • Senior Application Engineer as pre-sales/post sales/deployment
  • Work with various customers to help define their SpyGlass flows.
  • Key challenge was to adapt and customize these flows for each customer by understanding their present flows and make SpyGlass usage seamless.
  • Deploying SpyGlass tool suite (Lint, Clock Domain Crossing, Low-power, Power estimation, DFT checks, SDC Constraint checks) at customer sites.
  • Deliver presentation and trainings to the customers.
  • Provide technical assistance to customers.
  • Provide custom solutions which ease the tool adoption for the customer.
  • Supporting the sales team in technical product presentation and demonstration.
  • Have supported Atrenta customers worldwide, helped in tool evaluation at various customer sites resulting in getting multimillion dollar deals to the company.
  • Extensive multicultural experience, supported customers in China, Japan, France, UK, US.
SpyGlassLintClock Domain CrossingLow-powerPower estimationDFT checks+1

St microelectronics

Design Engineer

Jun 1999Jan 2005 · 5 yrs 7 mos · Noida, Uttar Pradesh, India

  • Design and Verification Engineer

Education

Aligarh Muslim University, Aligarh

Bachelor's degree — Electronics and Communication Engineering

Jan 1995Jan 1999

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