Hariharan M V — Software Engineer
Skilled in Full chip Physical Design, block level PnR and STA. Worked on Full chip integration Block level Physical Design implementation from RTL2GDSll Having tools exposure in ICC2, Fusion Compiler, PrimeTime & Calibre Handled multimillion's gate counted blocks Worked on 7nm, 5nm & 3nm.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bangalore Urban, Karnataka, India
Experience: 6 yrs 9 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Expert in Full chip Physical Design and integration.
- Proficient in advanced semiconductor technologies like 7nm and 3nm.
- Experienced with industry-leading tools like ICC2 and PrimeTime.
Work Experience
AMD
Senior Silicon Design Engineer (2 yrs)
Mirafra Technologies
Physical Design Engineer 2 (2 yrs 10 mos)
SMART VLSI
Physical Design Engineer (1 yr 11 mos)
Education
Bachelor of Engineering - BE at Coimbatore Institute of Technology