Taha Perwaiz

Software Engineer

Bengaluru, Karnataka, India2 yrs 3 mos experience

Most Likely To Switch

Key Highlights

Expert in physical design and timing closure.
Hands-on experience with cutting-edge semiconductor technologies.
Proven track record in complex SoC projects.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and VLSI technologies.

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Skills

Core Skills

Physical DesignTiming ClosureGraphics Hardware DesignDigital Ic DesignPower Performance Optimization

Other Skills

Full chip floorplanningECOTiming DRCFloorplanningPlacementRoutingAutomationManual interventionReshapingFeedthrough punchingIO pad placementGpuCache memoryPnrIcc2

About

As a Physical Design Engineer, I thrive on turning RTL designs into silicon reality. With a strong foundation in Synthesis, Floorplanning, Placement & Routing, Timing Closure, and DRC/LVS, I am eager to contribute to cutting edge semiconductor innovations. My enthusiasm for VLSI and semiconductor technology drives me to learn continuously, optimize designs, and tackle challenges head-on. I’m looking forward to collaborating with experts in the industry and making a meaningful impact in chip design.

Experience

2 yrs 3 mos

Total Experience

1 yr 1 mo

Average Tenure

1 yr 11 mos

Current Experience

Qualcomm

Physical Design Engineer

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India

Worked on cleaning 20k+ timing DRCs in two consecutive projects at SoC level; using both automation and manual intervention for 4nm projects.
Worked on floorplanning for Modem based chip on 3nm; involved in placement of macros, reshaping, feedthrough punching, IO pad placement, etc from scratch.
Worked on floorplanning of 4nm chipset for mobile based SoC.
Currently working on floorplanning of high end chipset for Snapdragon X series compute SoC.
Contributed in timing and DRC closure for a complex partition.

Full chip floorplanningECOTiming DRCFloorplanningPlacementRouting+2

Intel corporation

2 roles

Graphics Hardware Engineer

Mar 2024 – Jul 2024 · 4 mos · Bengaluru, Karnataka, India · Hybrid

GpuCache memoryGraphics Hardware Design

Physical Design Intern

Sep 2022 – Aug 2023 · 11 mos · Bengaluru, Karnataka, India · Hybrid

Working in Power Performance team (Physical Design) for “PnP - Power Estimation and Optimization” on Intel’s IPU/GPU project(s) using ICC, ICC2, PrimeTime PX, Perl, TCL and Low Power concepts.

Icc2Synopsys PrimetimePower Performance Optimization