M

Madhukar Yerraguntla

Software Engineer

Hyderabad, Telangana, India16 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in developing tools for chip verification.
  • PhD candidate focusing on secure compilation.
  • Best paper award recipient at ACM-IEEE conference.
Stackforce AI infers this person is a Semiconductor and Formal Methods expert with a focus on security and verification.

Contact

Skills

Core Skills

C/c++Static AnalysisFormal Methods

Other Skills

RustHaskellOcamlProgram repair toolsVerilogComputer-Aided Design (CAD)MatlabCProgrammingPythonControl Systems DesignSignal ProcessingEmbedded SystemsEmbedded CPspice

About

I am a Computer Science Engineer with experience in C/C++, Rust, Haskell and Ocaml languages. My interests lie in type systems, formal methods, programming languages for hardware and software development and as part of my work charter I developed tools for first time correct designs with emphasis on bug finding and security. I develop tools that aid in general chip/design verification including formal analysis, emulation, Fault injections etc. I am also well versed with Python, TCL and bash scripting. I have also dabbled in RTL writing, ABV, AMS verification and SPICE programming, primarily writing tools that work on such designs. I am experienced in functional programming, Static analysis and theorem proving in Coq. Some of the tools I developed include: 1. A vendor vendor-agnostic framework for memory emulation which is essentially an executable specification of the memories' address translation under an SoC. 2. A simulation based Fault injection tool for AMS/DMS designs that inserts multiple faults based on a fault specification into the design. It is primarily used by safety architects within NXP to verify the effectiveness of the safety architecture while re-using the functional tests. 3. An AMS assertion language that generated checkers for AMS designs that have better performance than SVA based checkers in terms of runtime overhead and expressibility. I am also a part-time PhD student at IIT Delhi working in the field of programming languages and formal methods. My PhD work focuses on secure compilation of synchronous reactive languages. By incorporating a Denning-style lattice-based secure information flow framework into a synchronous reactive data flow language, we provide a framework in which correct-and-secure-by-construction implementations for such systems can be specified and derived. In particular, we extend the Lustre programming framework with a security type system. The work is currently being formalized in Coq over Vèlus development. Publications: 1. S. Prasad, R. M. Yerraguntla, and S. Sharma. Security Types for Synchronous Data Flow Systems. In 2020 18th ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE), pages 1–12, 2020 (Best paper award recipient) 2. Sanjiva Prasad and R. Madhukar Yerraguntla. Normalising lustre preserves security. In Antonio Cerone and Peter Csaba Ölveczky, editors, Theoretical Aspects of Computing – ICTAC 2021, pages 275–292, Cham, 2021. Springer International Publishing (Best paper award nominee but did not win)

Experience

16 yrs 7 mos
Total Experience
7 yrs 8 mos
Average Tenure
1 yr 3 mos
Current Experience

Qualcomm

Staff Engineer

Feb 2025Present · 1 yr 3 mos · Hyderabad, Telangana, India · On-site

  • I am currently working as a Staff Engineer in Qualcomm Product Security Initiative (QPSI) group. My charter includes developing static analysis and program repair tools that find and fix security related bugs.
C/C++RustHaskellOcamlStatic analysisProgram repair tools

Freescale semiconductor

4 roles

CAD Design Engineer

Dec 2016Nov 2024 · 7 yrs 11 mos

  • I design and develop differential tools that aid in verification of designs specifically AMS designs.
VerilogFormal Methods

Design Engineer

Jun 2014Dec 2016 · 2 yrs 6 mos

  • I develop an in-house tool called Lancelot for Analog Mixed Signal designs that runs on various platforms including Verilog-AMS, Spice and Wreal.
  • I also am the in-house expert for formal verification of digital designs.
VerilogFormal Methods

Intern

Jun 2013Jul 2013 · 1 mo · Noida

VerilogFormal Methods

Intern

May 2012Jul 2012 · 2 mos · Noida Area, India

  • My work was on porting Assertions to the AMS domain and verifying Industrial IPs like ADC,LCD etc with the newly developed methodologies.
VerilogFormal Methods

Indian institute of technology, kharagpur

Student

Jul 2009Jun 2014 · 4 yrs 11 mos · Kharagpur Area, India

  • M.Tech in Control Systems Engineering and B.Tech in Electrical Engineering
VerilogFormal Methods

Education

Indian Institute of Technology, Delhi

Doctor of Philosophy - PhD — Computer Science

Jan 2017Jan 2022

Indian Institute of Technology, Kharagpur

Master's degree — Electrical and Electronics Engineering (Control Systems Engineering)

Jan 2009Jan 2014

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