Sachin Kumawat

Software Engineer

Delhi, India5 yrs 6 mos experience

Key Highlights

Expert in Formal Verification and Digital Hardware Design.
Led multiple successful FPV activities on complex IPs.
Recognized for excellence in Cache Memory and Mesh Controller projects.

Stackforce AI infers this person is a Formal Verification Engineer specializing in Digital Hardware Design.

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Skills

Core Skills

Formal VerificationDigital Hardware Design

Other Skills

Adobe PhotoshopChiselDebuggingFormal MethodsJasper GoldJavaLinuxPythonScalaSystemVerilogTCLVerilog

About

Experienced Formal Verification Engineer with a demonstrated history of working in the Verification industry. Skilled in SystemVerilog, Verilog, Chisel, Scala, Python,, Microsoft Office, and Java. Strong quality assurance professional with a BTech - Bachelor of Technology focused in Electrical engineering from Indian Institute of Technology, Delhi.

Experience

5 yrs 6 mos

Total Experience

1 yr 11 mos

Average Tenure

1 yr 7 mos

Current Experience

Microsoft

Formal Verification Engineer

Sep 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India · Hybrid

Intel corporation

2 roles

Formal Verification Lead

Mar 2024 – Sep 2024 · 6 mos · Bengaluru, Karnataka, India

Senior Formal Verification Engineer

Jan 2022 – Mar 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India

● My specialization involves scoping of HW designs, test plan creation, formal testbench coding, applying advance abstractions techniques to deal with design complexities, running formal coverage, applying deep bug hunting techniques, regression, scripting and mentoring team members on Formal methods
● My work include leading FPV activity on “Core Page Walker”, “Home Agent to resolve cache coherency”, “Mesh to Memory controller” IP and “Cache Memory” IP
● Received Divisional team award and DEG Group recognition award for Cache Memory IP
● Received Division recognition award for Mesh to Memory Controller IP
● Received Divisional team award for “Core Page Walker”

Formal MethodsDigital Hardware DesignFormal VerificationSystemVerilogChiselDebugging+4

Oski technology pvt ltd

Formal Verification Engineer

Jul 2019 – Oct 2020 · 1 yr 3 mos · Gurugram, Haryana, India · On-site

AXI-Interconnect
○ Formally signed off the design
○ Applied FIFO abstraction to resolve the complexity of the design
Rocket Chip Generator (Translation Lookaside Buffer)
○ Developed complete formal test plan for the design
○ Successfully implemented all checkers as well as constraints in Chisel; Applied abstraction to reach the required proof depth of the design
○ Exercised complete coverage to ensure exhaustiveness of the test bench

Formal VerificationChisel

Xerox

Internship

May 2016 – Jul 2016 · 2 mos · New Delhi

● NEET2 Program, Organized and executed a plan to increase the outreach of the internship program in all college campuses of Delhi covering 500+ students; Used Landing page and direct marketing to increase product sales
● TutorSpace Program, Managed big-data and analysis in company's flagship initiative in MOOC(Mass On-line Open Course) education; Used Canvas Instructure to manage the content of 100 members with editing and rendering