Mohit Negi

Software Engineer

Greater Delhi, Delhi, India14 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in validation of next-gen server products
  • Strong background in embedded systems and modeling
  • Proven track record in performance analysis and customer support
Stackforce AI infers this person is a Semiconductor and Embedded Systems expert with strong software development skills.

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Skills

Core Skills

SimicsComputer System ValidationPlatform ArchitectureC++

Other Skills

HFPGAHSLETLMSystemCPerformance AnalysisVLSIVerilogDigital DesignLinuxElectronicsPLCFPGAMicrocontrollersProblem SolvingDigital Electronics

Experience

14 yrs 1 mo
Total Experience
2 yrs 4 mos
Average Tenure
5 yrs 6 mos
Current Experience

Intel corporation

System Engineer

Oct 2020Present · 5 yrs 6 mos · Penang, Malaysia · On-site

  • Working on validation of next generation Intel Server products with team across different sites. My responsibility includes creating Hybrid platform which are based on Simics Virtual platform. The hybrid platform can be FPGA based or Co-emulation based depends on validation requirement. Our validation scope is from new memory subsystem to full multi core validation and also covering unique feature testing like thermal or stress test.
  • Also created hybrid platform-based FPGA and co-emulation environment with virtual platform running in Simics environment
SimicsComputer System ValidationHFPGAHSLE

Synopsys inc

Senior Research And Development Engineer 1

Dec 2016Sep 2020 · 3 yrs 9 mos · Noida Area, India

  • At Synopsys I am closely working with customer. I work primarily involves helping user in general debug using our tool, automating their setup using Tcl/Python, building their custom platfrom which they can use as starting point and resolving their tool related queries.
  • Performance analysis support – I have involved in a lot of performance analysis projects on Synopsys tool. Helping customer in achieving their performance number, Cycle model bring up along with workload bench marking, supporting Customer on vast Generic synposys IP like UMCLT2, CSI/DSI, DMAC.
  • Virtualizer Platform for Software development – I also closely working with an automotive company supporting its user across all geographies. My work involves helping user debug its Embedded Software, automating their test regression, Ramping up of new users.
  • I am also involved in onsite training session for new customer in India for Synopsys tool like Platform Architect and Virtualizer Studio.
C++TLMSystemCPlatform Architecture

Hcl technologies

Lead Engineer

Sep 2015Dec 2016 · 1 yr 3 mos · noida

  • systemc/tlm based modelling for embedded SW development and architecture exploration

Incise infotech private limited

2 roles

Team Leader-Modelling Engineer

Promoted

Jan 2014Jul 2015 · 1 yr 6 mos · Greator Noida

  • Virtual Prototype of Universal Flash Storage (UFS) 2.0 -
  • Overview-- Untimed functional LT based model of UFS system (host + device) with pre –existing UFS driver running on it.Integrating this UFS model into SoC virtual platform(QEMU or arm based)
  • My role-
  • modelling and verification of host controller, MIPI UNIPRO and integrating it with device controller made by other team members
  • Qemu based arm Emulator platform to be set up and booting the actual device driver on it .

Modelling Engineer

Oct 2013Jan 2014 · 3 mos · Greator Noida

  • WatchDog timer IP-
  • Developed tlm2.0 transaction based model for watchdog functionality.
  • Team building -
  • My responsibilities was to build a team of fresher which can used for later Virtual model development.this involved recruitment and training of team member .

Rf silicon/logic fab ,sks law associates

Engineering Intern

Jul 2012Oct 2013 · 1 yr 3 mos · Noida

  • BLUETOOTH LOW ENERGY CHIP (modelling)-
  • My responsiblities were Modelling of HCI layer in BLE .Modelling of stack from c++ to systemC and extending it till link layer (i.e host+hci+link layer).
  • USART with SPI supported IP (RTL+ verification + Modelling)
  • My role in this project was early on in RTL design of baud rate generator (Verilog) and then was later later involved in verification of the whole IP ..
  • Also developed LT model of the whole USART .

Cdac,noida

student

Aug 2011Mar 2012 · 7 mos · Noida, Uttar Pradesh, India

  • presently doing a six month diplomma course in vlsi and embedded system from cdac.

Education

suraj bhan dav, delhi

senior secondary — science

Jan 2005Jan 2006

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