Sep 2024 – Jul 2025 · 10 mos · Paris, Île-de-France, France

Sep 2021 – Jan 2025 · 3 yrs 4 mos · Paris

• Working on the Next Gen SuperComputer funded by the European Union

Feb 2019 – Aug 2021 · 2 yrs 6 mos · Hyderabad, Telangana, India

• Working on the next generation Discreet Graphics SOC System for Data Centre Applications (Ponte Vecco). I am involved in all stages of the Emulation builds and bring-ups. Some of the works done are building emulation models on Zebu, C++ and verilog based transactor integration, test case executions, reset bring-up. However my major focus was on PCIE bring-up in the discreet graphics system. Also worked on few Graphics based emulation test case executions. Helped debug many Road Blockers in the Emulation System.

May 2018 – Feb 2019 · 9 mos · India

• ● Part of Systems Engineering Team working on Algorithmic Development of next generation Advanced Driverless Assistance Systems(ADAS)
• ● Handle End-to-End implementation of In-House ADAS system on Xilinx Virtex Ultrascale FPGA, which is a Processor based design with DisplayPort, DDR and PCI being some of the major components.
• ● Also write Software application code for processor based designs on Xilinx Virtex Ultrascale FPGA device.

Dec 2014 – Sep 2017 · 2 yrs 9 mos

• ● Design/Debug, Report and Verify Issues in Hardware(Verilog) and SW (C) with Xilinx Video, DSP and Memory IP’s, thus release flawless Xilinx IP’s.
• ● Part of the Xilinx DisplayPort Application Note (XAPP1271 in C and Verilog) Design/Debug Team which is now used by Major customers like Christie Digital, Blackmagic, RGB, Olympus leading to annual Revenues averaging 10 million USD.
• ● Work with the Xilinx US Development Team to build/debug Video HW and Drivers (DP & HDMI), leading to many design wins, thus converting few competitor customers to Xilinx.
• ● Worldwide Highest Level Application Expert for DisplayPort IP Solution – Responsibilities include Identify and fixing Customer HW and driver issues, Drive Change Requests, Technical Documentation, Suggest Innovative Improvements for the IP, based on the Customer Usage requirements, Contribute as an expert to Internal Knowledge base forums and articles etc
• ● Project Lead/Champion for Christie Digital, where I coordinated implementation of the Xilinx Early Beta DisplayPort Solution in their project. Since this was an early beta release there were many challenges and issues with the customer implementation, which I got resolved through Customer Support Sessions and coordination between Cross Border R&D, Marketing and Field Teams.
• ● Primary contact for all the Video Connectivity and Processing IP solutions.
• ● Trained worldwide Applications team on the DisplayPort Protocol and IP in SanJose
• ● Organized the Worldwide Technical Sales Conference in Xilinx Hyderabad
• ● Part of the recruitment and Training Team for new Xilinx Engineers.
• ● Early beta design/support team for the HDCP IP, helping customers like Christie Digital
• ● Debug and support customer implementations of MIG IP for DDR2,DDR3 and DSP IP's
• ● Star Award for the best performer consecutively for 3 quarters.
• ● Was the representative from Xilinx India for the Worldwide Technical Sales Conference in Sanjose for the past 3 years (2015-2017) as a Video and DSP Specialist.

Apr 2013 – Dec 2014 · 1 yr 8 mos

• ● Breadth of Knowledge in FPGA Hardware Architecture - Internal routing, Memory, IO Logic, Gigabit Transceivers, IO Architecture, Power Design, Evaluation Boards Knowledge and Pin Mapping.
• ● As a Highest Level Expert in India for Gigabit Transceiver and IO, I implemented and debugged Xilinx Gigabit transceiver implementation issues on FPGA Hardware on Samsung Korea’s Boards, leading to a LTR of around 12 million USD
• ● Created a Patent on “Automatic Analysis, Detection & Correction of GT protocol based design issues using Embedded Processor based application” in 2017, which is under review at Xilinx.
• ● Helped Samsung design their board power components through use of Decoupling Capacitors for their Board Design applications using Xilinx FPGA. This project was a success and Samsung was able to bring out their board on Time leading to revenues and further confidence in Xilinx Solutions.
• ● Worked on a Hardware Board Simulation Project, along with other colleagues in the US, which involved running Emphasis and Equalization Sweeps in Agilent ADS and Hyperlynx Tools to validate the Xilinx IBIS and AMI model integrity.
• ● Trained the internal Team of around 20 Engineers on “Decoupling Capacitor Selections for Xilinx FPGA based boards” and “Signal Integrity Simulation of Xilinx FPGA based designs using Agilent ADS Tool”

May 2012 – Apr 2013 · 11 mos

• ● Breadth of Knowledge in Xilinx FPGA complete Flow cycle including ISE, Vivado, Implementation, Synthesis, Timing Constraints writing and Analysis, Chipscope, ILA, Fabric Architecture, Verilog/VHDL Coding, Debugging and Simulation.
• ● Was one of the local experts helping customers with writing Timing Constraints, Analyzing and Closing.
• ● Local expert for Verilog Coding implementation and debug with major customers like Samsung, Cisco, BlackMagic Design etc.
• ● Was working with worldwide customers supporting them with the implementation of their code on Xilinx FPGA’s using the Xilinx Tool Flow, leading to a 100% customers satisfaction for a consecutive 3 quarters and above 98% throughout the Year.
• ● Worked hand to hand with Cisco India(one of the top customers in India) during their Simulation of the Memory Interface for their design, leading to successful project completion without roadblocks in Simulation.

May 2010 – May 2012 · 2 yrs · India

• ● Writing Timing Constraints for Ericsson Charging Control Node based Design on Xilinx FPGA
• ● Verification using Simulations of the Designs in Verilog
• ● Star Award for the Best NCG in 2012

May 2009 – Oct 2009 · 5 mos

• 1) Worked on Noise modeling of All Digital Phase locked Loop of the Digital Radio Processor(Used as a transmitter in Mobile Devices) using Matlab. To verify the assumptions made by the matlab model, phase noise comparisons were made between the Matlab model and the actual model.
• 2) Identified few delay components which were missing from the Matlab model which helped bring the project back on track.