Adesh Sontakke — Engineering Manager

 24+ years of extensive industry experience in Building, Managing and Executing Multi-Core SoC Design Verification, PMIC (Power Management IC), MODEM SoC Verification, Mixed Signal RFIC SoC design & verification, IP Design Verification and Server CPU validation, and execution experience in DFx (DFT & DFD) and RTL to GDSII flow  Extensive ASIC verification experience in test bench component coding (BFM, monitors, scoreboards, checkers, assertions), writing test plans and testcases, testbench infrastructure development (scripting simulation/regression setup) and coverage tools (code coverage, functional coverage). Conversant with EDA tools and excellent analytical, programming skills (UVM, System Verilog, C, C++, Perl), Python  Experience in building and managing highly competent, high performance teams from scratch by hiring best talent in industry, mentoring and creating a close-knit unit. Good at project, schedule management and tracking.  Performed role of Verification & Validation Architect/DV Manager in multiple projects and Validation Architect. Involved in all stages of ASIC product life-cycle and part of many successful tape outs and enabled post-silicon validations.  Experienced in handling interactions with internal customers, EDA and Third Party vendors (including sub-contractor management). Team size handled: 65 team-members (max)  4 number of IEEE publications  2 granted USPTO patents Specialties: MultiCore SoC Verification/validation DFD (Design For Debug Verification), 10nm/7nm Storage-line server SoC Pre & Post Silicon Validation, Low Power Validation, PMIC-Power Management IC, Formal Verification, RF-Mixed Signal SoC design verification, Python RTL to GDSII execution, FUSE and SKU validation

Stackforce AI infers this person is a seasoned expert in semiconductor design and verification, specializing in RF and mixed-signal technologies.

Location: Bengaluru, Karnataka, India

Experience: 25 yrs 5 mos