Mranal K.

Software Engineer

Noida, Uttar Pradesh, India7 yrs 9 mos experience

Highly Stable

Key Highlights

5+ years of experience in SOC verification.
Led multiple successful chip tape-outs.
Published papers in Qualcomm's internal conference.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SOC and Analog Circuit Design.

Contact

Skills

Core Skills

Soc VerificationVerification MethodologiesAnalog Circuit Design

Other Skills

Serial protocolsSV/UVMC-based execution environmentPower Aware verificationAutomated model flowSerial Interface moduleVector developmentAMBA bus protocolsAnalog IO designSpice simulationsESD protection circuit designVLSIDigital DesignsSemiconductorsLayout Design

About

5+ years of experience working as SOC/Subsystem/IP DV Engineer for Mobile SOC, Modem, Auto and Compute chips at Qualcomm. Responsible for development of end-to-end test plan and strategy to verify complex blocks at SOC level. Experienced with development and enhancement of testbench at SOC level using C and System Verilog based verification environment. Hands on experience of working with GLS/SDF, coverage closure and power aware verification flow.

Experience

7 yrs 9 mos

Total Experience

7 yrs 9 mos

Average Tenure

7 yrs 9 mos

Current Experience

Qualcomm

4 roles

Staff Engineer

Dec 2025 – Present · 5 mos

Senior Lead Engineer

Promoted

Dec 2022 – Dec 2025 · 3 yrs

In addition to existing experience:
Responsible for IP level verification of Clock Controller as DL2.
Responsible for Sub-system verification of various CPU related tests such as interrupts, WFI etc.
Identifying the use case scenario for this new IP and test plan development (RTL, PARTL etc.) using SV/UVM and C based environment.

Senior Engineer

Dec 2020 – Dec 2022 · 2 yrs

Responsible for SOC verification of various serial protocols like I2C/I3C, SPI, UART and QSPI. Also working on SDCC (secure digital card controller) and eMMC (embedded multimedia card) for Mobile SOC, Modem, Auto and Compute chips.
SOC verification of serial interfaces, error scenarios etc. within safety subsystem for automotive chips.
Bring-up of test plan and execution environment for newly developed peripheral IPs using SV/UVM based test-bench and C based execution environment.
Worked on automated model flow (QSAM flow) for generating the C test cases.
Worked on PA (Power Aware)-RTL and PA-GLS and GLS/SDF verification.
Generation and execution of vector test suites (post silicon sequences) on tester along with complex vector debugs.
Leading and managing various activities at team level for successful chip tape out.
paper selected in verification track in Qualcomm internal conference QBUZZ 2021.

SOC verificationSerial protocolsSV/UVMC-based execution environmentPower Aware verificationAutomated model flow+1

SOC Verification Engineer

Jul 2018 – Nov 2020 · 2 yrs 4 mos

SOC Verification of Serial Interface module such as I2C, I3C, SPI, QuadSPI and UART.
Working on AMBA bus protocols (AHB, APB, AXI).
Responsible for vector development activity for peripherals and their successful on chip execution.
2 papers selected in verification track in Qualcomm internal conference QBUZZ 2020.
Won best paper in design verification track in Qualcomm internal conference QBUZZ 2020.

SOC verificationSerial Interface moduleVector developmentAMBA bus protocolsVerification methodologies

Sandisk®

Graduate Intern Analog Design

Jun 2017 – Jun 2018 · 1 yr · Bengaluru Area, India

> Analog IO design, working on 16 nm FINFET and 28 nm technology node.
> Designing of IO circuits such as core clamp ESD circuits, GPIO cells etc.
> Designing of high voltage tolerant ESD protection circuit in 16nm FINFET.
> Working on IO transmitter block in 16 nm.
> Spice simulations of various power ESD circuits for ESD test models, Leakage analysis, Inrush analysis etc.
> Design of low power and high speed Op-Amp using oxide TFT.

Analog IO designSpice simulationsESD protection circuit designAnalog Circuit Design