Govindan R — Software Engineer

Currently working as Engineer at L&T Technology services. - Brief Knowledge on PCIe Protocol - Good understanding on PCIe RAS, IDE, Hot plug. - Worked on Pre silicon verification of PCIe for the Intel Xeon data center products starting from test plan creation to execution, triage and debug across multiple milestones in Intel. - Exposure on CXL, HIOP, UCIe - Worked on X-Propagation debug challenges in GLS due to timing violations, uninitialized memory, and non- resettable flops. - Experience in Verification with good understanding of debugging skills on Cadence Incisive by using Verilog, System Verilog and UVM Methodology also had a hands-on experience in various protocols like AMBA Protocols, SPI, and Gate Level Simulation. Protocols: AXI, SPI, UART, PCIe, DDR and Ethernet Languages: Verilog, System Verilog. Methodology: UVM Programming Language : Python, perl

Stackforce AI infers this person is a Semiconductor Validation Engineer with expertise in PCIe and CXL protocols.

Location: Bengaluru, Karnataka, India

Experience: 4 yrs 9 mos