Vidyashree R S

Software Engineer

Bengaluru, Karnataka, India1 yr 6 mos experience

Key Highlights

  • Experienced in design verification methodologies.
  • Proficient in SystemVerilog and UVM.
  • Strong foundation in digital and analog electronics.
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and digital electronics.

Contact

LinkedIn

Skills

Core Skills

SystemverilogUniversal Verification Methodology (uvm)Digital Electronics

Other Skills

SVPerlC (Programming Language)C++Very-Large-Scale Integration (VLSI)Analog electronicsDigital CommunicationVerilog

Experience

1 yr 6 mos
Total Experience
1 yr 6 mos
Average Tenure
1 yr 6 mos
Current Experience

Mediatek

Design Verification Engineer

Oct 2024 – Present · 1 yr 6 mos · Bengaluru, Karnataka, India · On-site

SVPerlSystemVerilogUniversal Verification Methodology (UVM)C (Programming Language)C+++5

Maven silicon

Design verification trainee

Aug 2023 – Aug 2024 · 1 yr · Banglore · Remote

Digital electronicsVerilog

Education

Maharaja institute of technology mysore

Bachelor of Engineering - BE — Electronics and communication

Jun 2019 – Jun 2023

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