Naveen Bandaru

Software Engineer

Bengaluru, Karnataka, India5 yrs 1 mo experience
Highly Stable

Key Highlights

  • 4 years of experience in Design Verification.
  • Expert in SOC design verification methodologies.
  • Proficient in multiple verification protocols including AXI and PCIe.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SOC design and verification methodologies.

Contact

LinkedIn

Skills

Core Skills

Soc Design Verification

Other Skills

AXIVerilogAHBPCIeObject-Oriented Programming (OOP)SystemVerilogUniversal Verification Methodology (UVM)Digital Electronics

About

Have 4 yrs of experience in Design Verification. Worked in Qualcomm Client in multiple SOC projects

Experience

5 yrs 1 mo
Total Experience
2 yrs
Average Tenure
11 mos
Current Experience

Mediatek

Senior Design Verification Engineer

Jun 2025 – Present · 10 mos · On-site

Sivaltech

Senior Design Verification Engineer

May 2025 – Present · 11 mos · Bangalore Urban, Karnataka, India · On-site

Qualcomm

Design Verification Engineer

Jun 2022 – May 2025 · 2 yrs 11 mos · Bengaluru, Karnataka, India · On-site

  • Worked on Internet Protocol Accelerator (IPA) at SOC level. Functionally verified RTL test cases, Power Aware Simulations, Performance scenarios, Assertions and Coverage
AXISOC design verification

Cientra (an iso 9001:2015 company)

Design Verification Engineer

Oct 2021 – May 2025 · 3 yrs 7 mos · Bangalore Urban, Karnataka, India · On-site

AXIVerilog

Maven silicon

Design and Verification Trainee

Mar 2021 – Oct 2021 · 7 mos · Bangalore Urban, Karnataka, India

AXIVerilog

Education

Pragati Engineering College

Bachelor of Technology - BTech — Electronics and communication Engineering

Jan 2013 – Jan 2017

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