sreenivas k

CEO

Bengaluru, Karnataka, India19 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in SoC and Integrated Circuit Design.
  • Proficient in EDA tools and methodologies.
  • Strong background in Timing Closure and Formal Verification.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in EDA and Integrated Circuit Design.

Contact

LinkedIn

Skills

Core Skills

SocIntegrated Circuit Design

Other Skills

TCLSystemVerilogTiming ClosureEDASemiconductorsPerlCadence VirtuosoLogic SynthesisDebuggingFormal Verification

About

--

Experience

19 yrs 7 mos
Total Experience
4 yrs 10 mos
Average Tenure
7 yrs 9 mos
Current Experience

Intel corporation

Team Lead Manager

Jul 2018 – Present · 7 yrs 9 mos · Hyderabad, Telangana, India · On-site

SoCTCLSystemVerilogTiming ClosureEDASemiconductors+6

Amd

2 roles

MTS design engineer

Jan 2014 – Jul 2018 · 4 yrs 6 mos

PD sr.eng

Nov 2010 – Dec 2013 · 3 yrs 1 mo

  • Hi

Mindtree

PD @ sr.eng

Mar 2008 – Nov 2010 · 2 yrs 8 mos

  • --

Sasken

PD eng

Aug 2006 – Mar 2008 · 1 yr 7 mos

  • --

Education

vedaiit

pg dip — vlsi

Jan 2006 – Jan 2006

ECE nbkrist

Bachelor of Technology (B.Tech.)

Jan 2000 – Jan 2004

NEHS,cuddapah

NBKRIST — ece

Jan 2000 – Jan 2004

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