Khullar, Navneet — VP of Engineering
An Action and Growth oriented market focused Sr. Technology Executive in semiconductor industry with open and direct style of management, having multi-cultural global experience working in Top Semiconductor & IP companies Synopsys Inc., Virage Logic Corporation, NXP/Philips Semiconductors, Cadence Design Systems and ST Microelectronics in three continents (USA, Europe, Asia), with track record of successfully leading and creating high performance large engineering teams, size upto 700+ engineers in the area of Logic Libraries, IOs, Design Methodologies, Memories, System & SoC. Exposure to various aspects of the semiconductor business; strategy design, new technologies/products introduction, customer engagement, requirements management, specification definition, product life cycle, roadmap, application support and delivery Like to set high standards, goals and create a high energy challenging work environment with special focus on development of the team members and customer satisfaction. Key interest is in adding and creating value for all the stakeholders. Specialties: Developing and Leading Multi-cultural teams, People, Competence & Asset Management, Global Program & Product Management, Strategy Design & Execution, New Technology Introduction, Customer Engagement, Change Management during Mergers and Acquisitions (M&A), Semiconductor Product Engineering & Development, EDA Tools, Flows & Methodology, Operational & Business Excellence, Coaching & Mentoring
Stackforce AI infers this person is a Semiconductor Industry Executive with extensive experience in engineering leadership and product management.
Location: Sunnyvale, California, United States
Experience: 27 yrs 10 mos
Career Highlights
- Led engineering teams of over 700+ engineers.
- Expert in semiconductor product engineering and development.
- Strong focus on team development and customer satisfaction.
Work Experience
Synopsys Inc
Vice President of Engineering (1 yr 10 mos)
Executive Director, R&D Engineering (7 mos)
Sr. Director, R&D Engineering (3 yrs 8 mos)
Director of R&D (8 yrs 8 mos)
Virage Logic
Design Centre Head (1 yr 9 mos)
NXP Semiconductors
Sr. Engineering Manager (4 yrs 3 mos)
Engineering Manager (2 yrs 4 mos)
Technical Lead (2 yrs 4 mos)
Cadence Design Systems
Sr. Design Engineer (6 mos)
STMicroelectronics
Design Engineer (1 yr 11 mos)
Education
The Pentathlon - NXP Program for high Potentials at Ashridge Business School, UK
Executive Management at Columbia Business School
B.E. at Delhi Institute of Technology (Currently NSIT)
Executive Management at Indian School of Business