Rachit Dave

Software Engineer

Bengaluru, Karnataka, India10 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in CPU and Memory Architecture design.
Proven experience in VLSI and RTL logic design.
Strong background in semiconductor technology and memory compilers.

Stackforce AI infers this person is a Semiconductor Architecture Specialist with expertise in CPU and Memory Design.

Contact

Skills

Core Skills

Integrated Circuit DesignCpu ArchitectureMemory ArchitectureVlsi Design

Other Skills

CPU MicroarcLogic DesignRTL logic designCPU - L2 Mid level cacheSTOFetch and Decode unitMemory Compiler DesignMemory Development flow14nm finFET technologySRAM compiler40nm MOS technology28nm MOS technologyVLSIPhysical DesignVTCAD

About

Interested in Research & Development related work in Computer, Core (CPU/GPU) & Memory Architecture in Semiconductor domain.

Experience

10 yrs 9 mos

Total Experience

3 yrs 4 mos

Average Tenure

8 mos

Current Experience

Amd

Senior Member of Technical Staff

Aug 2025 – Present · 8 mos

CPU Microarc / Logic Design

CPU MicroarcLogic DesignIntegrated Circuit DesignCPU Architecture

Microsoft

Senior Logic Design Engineer

Oct 2024 – Aug 2025 · 10 mos

Intel corporation

2 roles

CPU L2 Cache Logic Design Engineer

Promoted

Aug 2017 – Oct 2024 · 7 yrs 2 mos

working as RTL logic designer for CPU - L2 Mid level cache

RTL logic designCPU - L2 Mid level cacheIntegrated Circuit DesignCPU Architecture

Core Datapath & Memory Desing Engineer

Feb 2016 – Aug 2017 · 1 yr 6 mos

Working as STO (section timing owner) for Fetch and Decode unit in Big Core team

STOFetch and Decode unitIntegrated Circuit DesignMemory Architecture

Synopsys

INTERN ( TECHNICAL R & D )

Jun 2014 – Feb 2016 · 1 yr 8 mos · Noida Area, India

Working as the Intern ( Technical R & D )
Working on Memory Compiler Design and Development flow
Project Completed :
ROM compiler, 14nm finFET technology.
Project Running :
SRAM compiler, 40nm MOS technology, high density Bitcell design.
SRAM compiler, 28nm MOS technology (TGO technology).
Work done during Project : ( Design and Analysis )
>>MOS characterization :
MOS/finFET capacitor characteristics analysis
Vt analysis
Leakage analysis
>>Bitcell Analysis : ( 6T SRAM and 8T SRAM )
Cell leakage current ( active and passive mode )
SNM
Read margin and Write margin
Read Current
>>Bitcell Array :
Array load model
Load reduction techniques
Leakage reduction techniques
>>Array Periphery :
Memory tracking circuit
Sense Amplifier ( improvement )
Address decoding
Power gating
GOALs :
Make better design (architecture) for very high speed memories for low Vt and low supply voltage.
Make better design for different Process variations on silicon.