Jun 2023 – Present · 2 yrs 10 mos

May 2014 – Jun 2023 · 9 yrs 1 mo

• Working on in-house tool development for Tegra SoC Physical Design. Following are some of the tools developed that are now widely used in building these complex SoCs.
• >> Full Chip Route Planning and Pinning Tool (Perl)
• >> Physical Planning and Implementation Tool for Control and Data Backbone Topology (Python)
• >> Logic Regioning Tool for Physical Implementation (Perl)

Aug 2011 – Apr 2014 · 2 yrs 8 mos

• Part of Nvidia ASIC-Physical Design team which is responsible for:
• >> Synthesis and Netlist Building
• >> Formality
• >> Floorplanning
• >> Static Timing Analysis
• As part of the team I have worked on:
• >> Static Timing Analysis :: Core, IO and Multi-Voltage Timing
• >> MTBF Analysis :: Equation to Flow
• >> Floorplanning :: Feedthrough and Grout based
• >> Synthesis :: Unit synthesis
• >> VT Selection for new nodes:: Power and Area optimized
• Apart from Static Timing Analysis, I am highly interested in the following topics which has resulted in some tools/experimentation/contributions that are now widely used in Nvidia :
• >> Power Estimation and Optimization :: Clock Tree Power Estimator
• >> Floorplan Optimization :: Floorplan Assistant and Grout Planner
• >> Metastability and MTBF
• >> Dynamic Thermal Management :: thermal experiments on multi-core Tegra chips