Ranjith R

CEO

Hyderabad, Telangana, India26 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in ASIC and SoC design and verification.
Led teams in developing next-gen Tegra chip technologies.
Proven track record in low-power design and FPGA prototyping.

Stackforce AI infers this person is a Semiconductor Engineering expert with extensive experience in ASIC and SoC development.

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Skills

Core Skills

AsicSocFpgaLow-power DesignVerificationDesign

Other Skills

Hardware DesignHardware ArchitectureFunctional VerificationRTL DesignDFTICVLSIVerilogEmbedded SystemsLogic SynthesisStatic Timing AnalysisDebuggingSimulationsSemiconductorsGatesim

Experience

26 yrs 1 mo

Total Experience

5 yrs 2 mos

Average Tenure

14 yrs 10 mos

Current Experience

Nvidia

Management

Jun 2011 – Present · 14 yrs 10 mos · Hyderabad

Responsible for delivering IO IP's like Ethernet , DSI , eMMC/SDMMC, *SPIx , low speed IO's , processor clusters for all of Tegra chips .
Owns , IP Architecture , design , unit verification and SOC Verification of these IP's
Was responsible for Unit FPGA prototyping for IO and Ultra Low Power IP's
Worked on System FPGA and Silicon bring up
Interfaced with SW and Customer teams to help solve customer issues
Owns design , verification , validation and architecture. Working on developing technology for the next generation Tegra chips for self driving ,gaming ,AI .
Actively involved in building teams and grooming leadership

ASICSoCHardware DesignHardware ArchitectureFPGAFunctional Verification+12

Amd

Manager ASIC/ Layout Design

Apr 2010 – Jun 2011 · 1 yr 2 mos

Responsible for Gatesim COE. This 26 strong team is responsible for SOC and IP level gatesim and PAG (power aware gatesim) across AMD . This team works with Fusion SOC's , servers as well as x86 and Graphics IP teams. Also responsible for driving the PAG and gatesim methodology for AMD

GatesimPAGSOCIPASIC

Soctronics

Project Lead

Oct 2007 – Mar 2010 · 2 yrs 5 mos

Lead the verification team for arc (www.arc.com) . The team was responsible for the complete verification activities for all the arc processor development. Activities involved , project planning for all the verification tasks , make sure that all the verification holes are covered. Also interact with other teams to make sure that the verification is done on time.
Lead the RCT ( Release Testing ) team for arc. The team responsibilty included testing of hardware ip's , codec's and tools of arc before it went to the customer. The tasks included undertanding of the different components in arc's engineering flow , co ordinate the release between US , UK and Russian offices and making sure that the release goes out with out a glitch
Was responsible for the complete RTL verification of AS211SFX which is one of the first sound to silicon solution in the industry. Also was responsible for the complete RCT activities for AS211SFX and all the related products and tools .

VerificationProject PlanningRelease TestingRTL Verification

Conexant systems

Senior Member Technical Staff

May 2004 – Sep 2007 · 3 yrs 4 mos

Worked on Design , Verification , STA , Synthesys , DFT and ATPG for modem soc's for conexant. And was responsible for the development of the test chip as well
Was involved in design , verification and gate level simulations for MFP related soc's . Also involved in support for FPGA and implementation activities .
Involved in multiple successful tape out of multimillion gate chips

DesignVerificationSTASynthesisDFTATPG

Portalplayer

Design Engineer

Nov 1999 – Mar 2004 · 4 yrs 4 mos

Was involved in design , verification , synthesis , sta , board activity etc for the audio soc's from Portalplayer. Worked extensively on low power designs and was involved in many successful tape outs.

DesignVerificationSynthesisSTA